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| orca orspi4 dual spi4 interface and high-speed serdes fpsc may 2009 data sheet ?2009 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 1 orspi4_07 1036-pin ftsbga devices have been discontinued. embedded spi4 core features oif-spi4-02.0 compliant interfaces dynamic timing receive interface: full bandwidth up to 450 mhz ddr (900 mbits/s) for all speed grades. bit de-skewing up to 16 phases of the clock capable of aligning bit-to-bit skews as large as ? bit periods static timing receive interface: speeds up to 325 mhz ddr (650 mbits/s), for all speed grades, including quarter-rate mode clock aligned or clock centered modes sup- ported dip-4 and dip-2 parity generation and checking transmit interface: speeds up to 450 mhz ddr (900 mbits/s) dedicated lvds transmit interface for improved data eye integrity automatic idle insertion 256 logical ports: embedded calendar-based sequence port poll- ing mechanism and bandwidth allocation. shadow calendar support for smooth transition to new calendar up to 32 independent tx and 32 independent rx buffers per spi4 interface internally. various aggregation modes to support 1 to 32 separate embedded buffers per tx and rx up to 4 independent tx and 4 independent rx clock domain transfers to the fpga logic fifo status support modes: 1/4 rate lvttl or 1/4 rate lvds automatic status handling or optionally under user control. credit calculations based on burst size and status are also handled automatically con?uration options as suggested in the oif- spi4-02.0 standard con?ures parameters such as maximum burst size, calendar length, main and shadow calen- dars (1k deep each), length of training sequence etc. simple fifo interface to the fpga logic provides ease of design and ef?ient clock domain transfers loopback modes provided for system- and chip-level debug embedded 32-bit internal system bus plus 4-bit parity interconnects fpga logic, microprocessor inter- face (mpi), embedded ram blocks, and embed- ded core blocks includes built-in system registers that act as the control and status center for the device low power operation. full-rate spi4.2 interfaces running at 450 mhz ddr (900 mbits/sec) with dynamic alignment consumes 1.5 w of power or less. more ef?ient than fpgas with soft-ip spi4 solutions which consume in excess of 10 w. programmable minburst capability with selectable burst values ranging from 16 to 240. interoperability demonstrated with orspi4 partners. embedded serdes core features quad 600 mbits/s to 3.7 gbits/s serdes: ieee 802.3ae xaui (link state machine & alignment fifos embedded) ansi x3.230:1994 1g/2g fc-compliant (link state machine & alignment fifos embedded) proven performance (same serdes used in ort82g5/ort42g5 fpscs) embedded memory controller features high performance memory controller for interface to external buffer memory required for layer 2 data buffering qdr ii memory interface: 36-bit input and 36-bit output bus, 18-bit address 175 mhz clock rates 20+ gbits/s bandwidth supports 2- or 4-word burst mode simple fifo interface to fpga integrated pll for optimized performance proven performance with multiple memory suppliers note: the term spi4 refers to oif spi-4.2 throughout this document lattice semiconductor has developed a next-generation fpsc targeted at high-speed data transmission. built on the series 4 recon?urable embedded system-on-a-chip (soc) architecture, the orspi4 fpsc contains two spi4.2 interface blocks, a high-speed memory controller, four channels of 0.6-3.7 gbits/s serdes with 8b/10b encoding and decoding and over 600k programmable system gates all on a single chip.
lattice semiconductor orca orspi4 data sheet 2 1036-pin ftsbga devices have been discontinued. high-speed orca series 4 fpga internal performance of > 250 mhz over 16k programmable logic elements 1.5v operation (30% less power than 1.8 v operation) comprehensive i/o selections including lvttl, lvcmos, gtl, gtl+, pecl, sstl3/2, hstl, zbt, ddr, lvds, bused-lvds, and lvpecl 1036-pin ftsbga package provides enough fpga user i/os (498) for 4 full-duplex xgmii interfaces, 4 full-duplex pl-3 interfaces, etc; a 40% smaller 1156-pin fpbga package is available with 356 fpga user i/os. note: 1036-pin ftsbga discontinued per pcn#06x-09. introduction the spi4 blocks provide dual 10 gbits/s physical-to-link layer interfaces in conformance to the oif-spi4-02.0 speci?ation. each block provides a full-duplex interface with an aggregate bandwidth of 13.6 gbits/s. this is achieved by using 16 lvds pairs each for rx and tx operating at a maximum data rate of 900 mbits/s with a 450 mhz ddr clock. both static and dynamic alignment are supported at the receive interface. dynamic alignment is used to compensate for bit-to-bit skew at higher data rates, where it becomes dif?ult to meet tight setup/hold requirements. dip-4 and dip-2 parity generation and checking are supported. data buffering of 8k bytes for both transmit and receive is provided by embedded dual-port ram in each spi4 core. internal 1k deep main and shadow calendar supports scheduling of up to 256 ports. the transmit and receive status fifos can also store ?w control information for up to 256 ports, the maximum speci?d in the spi4 speci?ation. an independent qdrii memory controller block provides data buffering between the fpga logic and external memory and supports a throughput of greater than 20 gbits/s. data is transferred to and from memory through two sets of 36-bit unidirectional data lines operating at up to 175 mhz ddr. a set of 72 data signals is available to transfer data across the core-fpga interface and allows the system to utilize the bandwidth available with second- generation quad data rate (qdrii) srams. of the 72 data signals, 8 signals can be either used for parity or data. a soft ip version of this core is also available to allow a second data buffer on this device. the high-speed serdes block supports four serial links, each operating at up to 3.7 gbits/s (2.96 gbits/s data rate with 8b/10b encoding and decoding), to provide four full-duplex synchronous interfaces with built-in rx clock and data recovery (cdr) and transmitter preemphasis. the serdes block is identical to that in the ort82g5 fpsc, supports embedded 8b/10b encoding/decoding and implements link state machines for both 10g ethernet, and 1g/2g/10g fibre channel. the state machines are ieee p802.3ae/d4.01 xaui based and also support fc (ansi x3.230:1994) link synchronization. table 1. orca orspi4 ?available fpga logic note: the embedded core, embedded system bus, fpga interface and mpi are not included in the above gate counts. the system gate ranges are derived from the following: minimum system gates assumes 100% of the pfu's are used for logic only (no pfu ram) with 40% ebr usage and 2 pll's. maximum system gates assumes 80% of the pfu's are for logic, 20% are used for pfu ram, with 80% ebr usage and 4 pll's. the orspi4 device is offered in two packages: 1036 ftsbga and 1156 fpbga. the 1036 package offers 498 fpga user i/os while the 1156 package offers 356 fpga user i/os. additionally, the serdes option is not available on the 1156 package. device pfu rows pfu columns total pfus fpga max user i/o luts ebr blocks ebr bits (k) usable* gates (k) orspi4 46 44 2,024 498/356 16,192 16 148 471-899 lattice semiconductor orca orspi4 data sheet 3 1036-pin ftsbga devices have been discontinued. orspi4 overview the orspi4 fpsc provides two spi4.2 interface blocks, a memory controller and a 4-channel serdes block, combined with fpga logic. based on the 1.5 v or4e06 orca fpga, it has a 46 x 44 array of programmable logic cells (plcs). the embedded core is attached to the right side of the device, as shown below, and is inte- grated directly into the fpga array. a top level diagram of the basic chip con?uration is shown in figure 1. figure 1. orspi4 basic chip con?uration each of the logic blocks in the embedded core is functionally independent from the other blocks. connections between blocks must be made through the fpga logic. however, one of the spi4 blocks and the serdes block share i/os. hence the device may be con?ured to provide either two spi4 interfaces or one spi4 interface and one serial interface. what is an fpsc? fpscs, or field-programmable system chips, are devices that combine ?ld-programmable logic with asic or mask-programmed logic on a single device. fpscs provide the time to market and the ?xibility of fpgas, the design effort savings of soft intellectual property (ip) cores, and the speed, design density, and economy of asics. fpsc overview lattice s series 4 fpscs are created from series 4 orca fpgas. to create a series 4 fpsc, several columns of programmable logic cells are integrated with an embedded logic core. other than replacing some fpga gates with asic gates, at greater than 10:1 area ef?iency, none of the fpga functionality is changed?ll of the series 4 fpga capability is retained including the embedded block rams, microprocessor interface (mpi), boundary scan, etc. pins from the replaced columns of programmable logic are used as i/o pins for the embedded core. the remainder of the device pins retain their fpga functionality. fpsc gate counting the total gate count for an fpsc is the sum of its embedded core (standard-cell/asic gates) and its fpga gates. because fpga gates are generally expressed as a usable range with a nominal value, the total fpsc gate count is sometimes expressed in the same manner. standard-cell asic gates are, however, 10 to 25 times more silicon- orca 4e06-based programmable logic embedded core fpga programmable i/o spi4.2 i/f spi4.2 i/f memory quad serdes spi4 i/o spi4 i/o memory controller serial i/o / controller i/o shared i/o lattice semiconductor orca orspi4 data sheet 4 1036-pin ftsbga devices have been discontinued. area ef?ient than fpga gates. therefore, an fpsc with an embedded function is gate equivalent to an fpga with a much larger gate count. fpga/embedded core interface the interface between the fpga logic and the embedded core has been enhanced to allow for a greater number of interface signals than on previous fpsc architectures. compared to bringing embedded core signals off-chip, this on-chip interface is much faster and requires less power. all of the delays for the interface are precharacterized and accounted for in the isplever development system. series 4 based fpscs expand this interface by providing a link between the embedded block and the multi-master 32-bit system bus in the fpga logic. this system bus allows the core easy access to many of the fpga logic func- tions including the embedded block rams and the microprocessor interface. clock spines also can pass across the fpga/embedded core boundary. this allows for fast, low-skew clocking between the fpga and the embedded core. many of the special signals from the fpga, such as done and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the fpga as a system. for even greater system ?xibility, fpga con?uration rams are available for use by the embedded core. this allows for user-programmable options in the embedded core, in turn allowing for greater ?xibility. multiple embed- ded core con?urations may be designed into a single device with user-programmable control over which con?u- rations are implemented, as well as the capability to change core functionality simply by recon?uring the device. fpsc design kit development is facilitated by an fpsc design kit which, together with isplever and third-party synthesis and sim- ulation engines, provides all software and documentation required to design and verify an fpsc implementation. included in the kit are the fpsc con?uration manager, and compiled verilog simulation models, hspice and/or ibis models for i/o buffers, and complete online documentation. the kit's software coupled with the design envi- ronment, provides a seamless fpsc design environment. more information can be obtained by visiting the lattice website at http://www.latticesemi.com . spi4 protocol overview the system packet interface level 4, phase 2 (spi4) was de?ed by the optical internetworking forum (oif) as an interface for packet and cell transfers between a physical layer (phy) device and a link layer device for applica- tions requiring up to 10 gbit/s aggregate bandwidth. the system level model for the spi4 interface is shown in fig- ure 2. lattice semiconductor orca orspi4 data sheet 5 1036-pin ftsbga devices have been discontinued. figure 2. system model for spi4 interface the details of the interface are speci?d in the oif document ?mplementation agreement oif-spi4-02.0 (www.oiforum.com). that speci?ation is based on the system model shown in the previous ?ure, which, in turn, is based on the open system interconnect (osi) reference model. in the system model, a ?ransmit interface sends address, start and end of packet signals and error control information from a link layer device to a phy device and receives ?w control (status) information from the phy device. in the other direction, a ?eceive interface at the link layer receives data from a phy device and sends status information to the phy device. while this convention provides a clear framework for de?ing the system level functions, a clean separation between link layer and physical layer functionality is not often seen in actual implementations. the orspi4 fpsc spi4 blocks implement the basic functions de?ed in the standard and also implements addi- tional options, as suggested in the standard, to con?ure parameters such as maximum burst size, calendar length, length of training sequence, etc. as required by the speci?ation, the transmit and receive interfaces oper- ate completely independently. receive link layer device physical (phy) layer device tstat[1:0] tsclk tdclk tdat[15:0] tctl rstat[1:0] rsclk rdclk rdat[15:0] rctl phy layer in model link layer in model transmit link layer device lattice semiconductor orca orspi4 data sheet 6 1036-pin ftsbga devices have been discontinued. embedded core overview - functions and features the embedded core contains four separate functional blocks, two spi4 interface blocks, a high-speed memory controller block, and a quad serdes block providing 4 channels of 0.6-3.7 gbits/s serdes. features common to all blocks include: improved powerpc ? 860 and powerpc ii high-speed synchronous microprocessor interface that can be used for con?uration, readback, device control, and device status; as well as for a general-purpose interface to the fpga logic, rams, and embedded standard cell blocks. glueless interface to synchronous powerpc processors with user-con?urable address space provided. new embedded amba speci?ation 2.0 ahb system bus ( arm processor) facilitates communication among the microprocessor interface, con?uration logic, and embedded core blocks. fpsc design kit available for use with isplever development system software. supported by industry-stan- dard cae tools for design entry, synthesis, simulation, and timing analysis. spi4 interface blocks - overview the orspi4 fpsc provides two independent spi4 interface blocks in the embedded core. the two spi4 blocks are identical and the following overview applies to both blocks. in the following sections, the spi4 protocol conven- tions for ?ransmit and ?eceive are not followed, since in various applications the orspi4 fpsc could be used to perform different functions at various levels in the spi4 protocol stack. instead, the ?ransmit functions are those used to transmit data to and receive current status information from the device at the other end of the spi4 link. the ?eceive functions are those used to receive data from and transmit current status information to the device at the other end of the spi4 link. each spi4 block supports a standard 10 gbits/s physical-to-link layer interface in conformance to the speci?ation. this is achieved by using 16 lvds pairs each for rx and tx that operate at a maximum data rate of 900 mbits/s with a 450 mhz ddr clock. data buffering of 8 kbytes each in the transmit and receive direction (example: 256 bytes each for up to 32 ports) is provided by embedded dual-port ram (dpram). aggregation of buffer space is supported for systems with less than 32 ports. the internal calendar and transmit and receive status fifos have been sized so that applications with larger numbers of ports can be supported. the orspi4 has been designed to support up to 256 ports, the maximum speci?d in the spi4 speci?ation. despite operating independently, both the transmit path and the receive path logic perform similar functions and the partitioning of both logical blocks are quite similar as shown in figure 3. the top level partitioning is between the logic blocks to transfer and process data and control information, and the logic blocks to generate, transfer and process status information. spi4 interface block features each spi4 block provides a standard 10 gbits/s physical-to-link layer interface in conformance to the oif-spi4- 02.0 speci?ation. each interface provides an aggregate bandwidth of 13.6 gbits/s. this is achieved by using 16 lvds pairs each for rx and tx with a maximum data rate of 900 mbits/s using a 450 mhz ddr clock. the blocks can be used for applications such as interconnecting an oc-192 framer with a proprietary packetized interface, to a network processor with a spi4 based packet interface or vice versa. support for ?tatic or ?ynamic alignment at the receive interface. at clock rates above 350 mhz ddr, it becomes dif?ult to meet the tight setup/hold requirements at the receiver using static alignment. in this case, dynamic alignment is used to compensate for bit-to-bit skew. dynamic alignment automatically compensates for process, voltage, and temperature (pvt) changes in devices and systems. full bandwidth up to 450 mhz ddr (900 mbits/s throughput) dynamically performs alignment based on 16 phases of the rx clock for improved accuracy alignment algorithm can be done based on excessive bit errors on the dip-4 calculation clock skews up to +/- one clock cycle can be compensated by the dynamic alignment logic lattice semiconductor orca orspi4 data sheet 7 1036-pin ftsbga devices have been discontinued. for low speed data, static alignment can be selected through a programmable control bit speeds up to 350 mhz ddr (700 mbits/s throughput) dynamic alignment is bypassed and disabled to save power in static alignment mode. programmable on-edge or on-center clock/data relationship option at receiver. programmable clock delay single-link and multi-link operation. spi4 transmit data protocol support logic combines the data and control words from the transmit fifo (dprams) into the spi4 format performs dip-4 calculation over data and control words on the tx side and inserts into the payload control word handles all credit calculations based on the status information automatically provides optional signals to fpga interface logic for ?w control: current transmit port id (calendar port or user speci?d port # per calendar port) current burst_val parameter for that port status from that port embedded calendar-based port polling sequence mechanism and bandwidth allocation for all 256 ports programmable transmit and receive calendar tables support up to 256 ports two calendars are supported in each direction main calendar (1k deep) shadow calendar (also 1k deep). user can recon?ure second calendar while operating off main calendar, and then switch on the next cycle to allow hitless operation all calendar con?uration parameters speci?d in the standard (calendar_len, calendar_m, etc.) are supported transmit and receive status fifos provided to store ?w control information for up to 256 ports. performs status frame creation dip-2 odd parity calculated over the status frames supports either quarter-rate lvds or lvttl status channels support for various options for ?w control status creation, selectable per port: based on dpram fifo ?l levels based on status from fpga interface per port both of the above dual-port ram interface to the fpga supports ?xible data widths for both the receive and transmit fpga/core interfaces. scalable data bus enables users to con?ure tx interface for their respective port bandwidth requirements a total of 4 dpram banks where each of the dprams can be logically partitioned into 1, 2, 4, or 8 virtual fifos used for temporary storage and clock domain crossing can be con?ured to provide 32-, 64-, 128-bit data bus interfaces from the fpga (plus accompanying con- trol signals) 32-bit mode: four banks are separate and accessed independently 64-bit mode: banks 0 & 1 become a single aggregation and banks 2 & 3 become a single aggregation 128-bit mode: all four banks become a single aggregation mixed mode: one 64-bit (two banks become a single aggregation) and two banks are separate and accessed independently training pattern generation user controlled ?lpha repetitions of training pattern in tx_data_max_t intervals automatic generation of training pattern during loss of synchronization lattice semiconductor orca orspi4 data sheet 8 1036-pin ftsbga devices have been discontinued. automatic idle generation when no data for a given channel is available for transmit if the receiver on other end of the link is ?atis?d for this channel automatic training pattern and idle deletion in receive path low-power, high performance asic lvds i/os compliant with eia -644 i/o buffers support hot insertion i/o buffers proven to operate at over 900 mhz rates (lattice orli10g fpsc uses same lvds buffers) on-chip center tap termination for common mode noise reduction con?uration options as suggested in the oif-spi4-02.0 standard are supported to con?ure parameters such as maximum burst size, calendar length, length of training sequence, etc. support for three forms of loopback: high-speed near end loopback which involves looping back data from the high-speed transmit block serial output to the high-speed receive block serial input. all of the logic up to the lvds buffers is included in the loopback path. the lvds buffers are bypassed far end loopback which involves looping back the 128-bit output data from high-speed receive block to the 128-bit input of the high-speed transmit block. data is received at the high-speed spi4 rx interface and transmitted at the spi4 tx interface. the transmit protocol, receive protocol and dpram blocks are bypassed. this works for both static and dynamic alignment modes. low-speed near end loopback which excludes the high-speed blocks from the loopback path. this involves sourcing data from the fpga, looping back the output of the transmit protocol block into the receive protocol block and observing data at the core-fpga boundary support for several spi4 debug options: under software control, dip-4 errors can be forced by inverting the dip-4 parity bits dip-2 errors can be forced by inverting the dip-2 parity bits eight-bit counters are provided for counting dip-4 and dip-2 errors spi4 status reporting capabilities: status information is reported through status registers. most conditions can also cause an alarm (interrupt) to be generated dip-4, dip-2 errors deskew error from high-speed rx side dpram virtual fifo overruns lattice semiconductor orca orspi4 data sheet 9 1036-pin ftsbga devices have been discontinued. figure 3. orspi4 spi4 interface block - top level functional partitioning at the embedded core/fpga interface, data buffering is provided by banks of dpram partitioned into fifos. fifo reads and writes are completely decoupled. data and accompanying address, packet delineation and error identi? cation information are written into the selected fifo as received - either from the fpga, in the transmit case, or from the receive link. for transmit, reads are performed from the fifos based on pre-programmed packet format information, a pre-programmed schedule for link access as read from calendar logic, and far end status information as received from the transmit status logic. in the receive direction, the receive status logic transmits information concerning the states of the receive buffers on the receive status links, while the fpga logic reads data from the fifos as needed under control of the fpga logic. the read/write control functions are similar if operating with external ram. in this case, the internal dpram can be used as clock domain crossing fifos. formatting/deformatting, ?w control processing, and error control logic forms the interface between the dpram banks and the spi4 transmit and receive blocks. this logic performs the necessary conversions between the spi4 and fpga/core interface formats. it also performs dip-2 (status) and dip-4 (control) generation/checking. finally, the spi4 interface blocks perform the mux/demux functions for rate conversion between the internal core data paths and the spi4 links and also provides the needed lvds driver and receiver functions. either static or dynamic alignment is available at the receiver interface. dynamic alignment is used to compensate for bit-to-bit skew at higher data rates where it becomes dif?ult to meet tight setup and hold timing requirements. input protocol spi4 logic - status transmit receive output protocol spi4 logic - data output protocol spi4 logic - status input protocol spi4 logic - data dpram write transmit buffers port calendar read control control banks descriptor address sequencer map transmit data transmit status transmit control fifo_full 32, tstat[1:0] tsclk tdclk tdat[15:0] tctl rstat[1:0] rsclk rdclk rdat[15:0] rctl dpram receive buffers banks calendar port status sequencer 64, 128 receive status transmit buffers port descriptor address map read data 128 read control write receive control center lattice semiconductor orca orspi4 data sheet 10 1036-pin ftsbga devices have been discontinued. spi4 transmit path overview the ?st of the major blocks in the transmit section contains four dpram banks which can be con?ured to provide 32-bit, 64-bit or 128-bit data bus interfaces from the fpga to the embedded core. providing a scalable data bus enables users to tailor the transmit interface to meet their port bandwidth requirements. for example, with a pos- phy level 3 (pl3) interface supporting multiple phys (ports), a single 32-bit interface to the transmit dpram is required. for an ethernet 10 gbits/s interface, a single port will require a single 128-bit interface to the transmit dpram. to realize the various data bus interfaces or aggregation modes, the user must con?ure the mode within the embedded core via the mpi interface or the system bus. multiple dpram banks can be aggregated into larger fifos. division of the dpram banks into virtual partitions (up to eight) is also possible. the fpga logic initiates a write to dpram by providing data, port id, 3-bit fifo address and write enable signals to the spi4 block. the internal fifo controller latches the data and port control information into a temporary hold register that stores the data until an entire 128-bit line is captured, or an eop is asserted. the 128-bit line is then written into the selected virtual fifo. associated with each fpga data write interface, there are also control information signals and a transmit clock. the fifo control logic transparently passes the control information to the control memory, with the exception of the byte enable bits (be[3:0]), which indicate which bytes of the associated 32-bit word are valid. the dpram read logic blocks poll port data from the dpram banks, based on a precon?ured calendar sequence and the current status of each active port. the spi4 calendar is a mechanism that maintains out-of-band statistics of the current status of each port supported across the spi4 interface. the calendar is a reverse direction ?w-con- trol mechanism used to control the dynamic bandwidth allocated for the each supported port. by periodically pro- viding far end receive status for each port, the transmitter can modulate the amount of bandwidth allocated to a particular port dynamically. writes to the dprams from the fpga logic are asynchronous to the calendar polling algorithm. the spi4 transmit logic reads data from the dprams according to a strict calendar sequence algorithm and will generally not read port data from the virtual fifos in the sequence it was written. both a main and a shadow calendar are provided and are each 1k deep. this enables the user to provide ?er granularity of the polling sequence based on bandwidth allocated for each port. the length of the calendar table (calendar_len) is programmable. calendar_len should be at least as large as the number of active ports (channels) in the system and should not exceed the upper threshold set by the parameter (max_calendar_len). there are two basic modes supported for transmitting data. within the spi4 core, the embedded core operates identically for all modes. at the fpga interface, processing will be done slightly differently, depending upon the mode the user requires. each mode is discussed below. embedded memory mode - this mode is used when the orspi4 is interfacing to asynchronous fpga inter- faces, such as pos-phy level 3, 1gbe, utopia level 3, etc. and storing the data in the virtual dpram fifos. when operating in this mode, the spi4 transmit logic will read port data from the fifos according to the calendar sequence. if there is no data, it will send idle data and advance to the next port. it is the user's responsibility to ensure the proper port data has been written to the virtual fifo. external memory mode - this mode is used in conjunction with the memory controller or some other external memory based interface where data is available only after some ?ed delay. in this mode the spi4 transmit logic instructs the fpga as to what port data to retrieve as well as how many bursts of data to retrieve. the fpga is responsible to write the data read from the memory controller into the dprams. data is read from the dpram devices by the spi4 transmit logic according to the transmit calendar. the dpram read logic also includes a port descriptor memory (pdm) which is a user con?urable memory con- taining a list of read control parameters for all enabled ports to be polled. the depth of the memory is 256 locations, lattice semiconductor orca orspi4 data sheet 11 1036-pin ftsbga devices have been discontinued. which corresponds to the maximum number of ports that are supported by spi4. the pdm data is comprised of three separate segments - a 10-bit dynamic table maintained by the spi4 logic, a static 20-bit table, and a dynamic 3-bit register ?e written by the fifo status update (fsu) logic. the pdm provides a mapping of the spi4 port number to the fpga interface device/port number, removing the burden from fpga logic. when port data is read from the pdm, a status update bit (the u-bit) is ?st examined to see whether the stat ?ld is new or stale. if stale, then the stat ?ld is not considered for the rest of processing. if the stat ?ld is new (u- bit=1) the stat ?ld is used in conjunction with other ?ld to calculate what the new credit ?ld for the port should be. a satisfied status indicates the corresponding port's fifo is almost full, and only transfers using the remaining previously granted 16-byte blocks (if any) may be sent to corresponding port until the next status update. no addi- tional transfers to that port are permitted. when a hungry status indication is received, transfers up to maxburst2 16-byte blocks or the remainder of what was previously granted (whichever is greater), may be sent to the corresponding port prior to the next status update. a starving status indication indicates that buffer under?w is imminent in the corresponding phy port. when starving is received, transfers for up to maxburst1 16-byte blocks may be sent to the corresponding port prior to the next status update. if the u-bit is cleared, this indicates the stat ?ld has already been used to update the credit ?ld on a previous port servicing. therefore, the credit ?ld should simply be reduced by burst_val. otherwise, the credit ?ld is updated to the new credit value minus burst_val. in both cases, the output of the logic is used to update the credit ?ld. if the credit ?ld is zero, and the stat ?ld is stale, then the port receives no service. read accesses of the port control information need to be optimized to minimize any lost bandwidth due to the credit ?ld having a value of zero. data read from the dprams is sent to the spi4 transmit block which is responsible for the following functions: combining the data and control words from the transmit fifo into the data format speci?d in the oif spi4 standard. dip-4 calculation and insertion into the payload control word. generation of idle/training control words in programmable intervals. training words are used to dynamically align the far end receiver. as long as a disabled status ?1 is received on the spi4 status channel, the transmit interface block sends continuous training patterns (10 training control words followed by 10 training data words). when valid status is received on the status channel, user data is normally sent on the spi4 data link. however, users can also periodically schedule training patterns in tx_data_max_t peri- ods. the training patterns can be repeated tx_alpha times. both tx_alpha and tx_data_max_t are pro- grammable control register bits. the spi4 transmit block contains the high-speed serializer which uses the x8 clock, synthesized by an internal pll, to generate the high-speed data from the low-speed 128-bit fifo data. data is transmitted off-chip using a 16-bit lvds data bus - tdat[15:0], a lvds control bit - tctl, and a source synchronous clock - tdclk. the 16-bit data bus and control are ddr with respect to tdclk. in order to support 10 gbits/s throughput, the minimum frequency of tdclk needs to be 622 mbits/s (311 mhz ddr). to allow considerable margin above this minimum data rate a maximum frequency of operation of 900 mbits/s is supported. the transmit status protocol (s4tsp) block provides the interface to the spi4 transmit status interfaces. these signals can be either lvds or lvcmos buffers. the s4tsp block is responsible for the following functions: fifo status decoding and buffering. framing using the status framing pattern. dip-2 checking of incoming status information. lattice semiconductor orca orspi4 data sheet 12 1036-pin ftsbga devices have been discontinued. the fifo status update logic block reads the port and status information and uses this information to update port descriptor memory stat ?ld. whenever a valid stat ?ld has been updated, the associated u-bit ?ld is set as discussed previously. this indicates that the stat ?ld is new and that the credit ?ld for that must be re-evaluated the next time it is selected as a source for transmit data. spi4 receive path overview in the receive direction, data is received in spi4 format on the lvds i/os at the receive interface. the data is writ- ten into dpram as received and read from the dprams as requested by the fpga logic. control information is also interpreted and buffered and idles and training sequences are removed from the incoming data stream. receive fifo status is transmitted from the receive status interface according to a pre-con?ured polling sequence contained within the receive calendar. data is formatted into the spi4 receive status format and sent to the physical links as either lvds or lvttl signals. the spi4 block contains the high-speed receive logic. incoming lvds signals, in spi4 format, include the 16-bit data bus (rdat[15:0]), a control bit (rctl) and a source synchronous ddr clock (rdclk). the incoming data is deserialized to a 128-bit format and the control information is converted to an 8-bit format. the spi4 receive block also detects training patterns and performs dynamic alignment of the incoming data. at speeds above 700 mbit/s (350 mhz) it becomes necessary to use dynamic alignment. skews of up to ?one clock period can be compensated by the dynamic alignment logic. for low speed incoming data, static alignment can be chosen through a programmable control bit. various timing options of receive data vs. receive clock are also pro- grammable. the spi4 block is responsible for decoding the in-band control information. it then forwards both the data and con- trol information, such as link address, sop, eop and error, to the virtual fifos. the spi4 block also parses the control words embedded within the incoming data. using this control information, it performs the following func- tions: checks dip-4 parity monitors for continuous alignment (if more than a programmable number of dip-4 parity errors exist, there may be an alignment problem). removes idle/training words. extracts link address and sop, eop and valid packet (no error) signals. in the receive direction there are also four dual port memory (dpram) banks that contain a total of 8k bytes avail- able for clock domain crossing and/or temporary buffering. as with the transmit buffers, each bank can be further partitioned up to 8 virtual memories, one for each of 8 ports. the following are the characteristics of the dpram virtual fifos: the dpram memories support asynchronous reads. each dpram bank can be accessed on the fpga side with an individual clock. for data buffering beyond 32 ports, the dpram banks can be used as clock domain crossing fifos before writ- ing the data and control information into an external memory. if fewer ports are supported, the virtual memories can be aggregated, providing more buffer space for each port. each dpram bank has a 32-bit data and 8-bit control read interface to the fpga. when using the dpram memories, the data can be read as either a 32-, 64-, or 128-bit data bus with associated control signals. at any time, the user can poll the status of a fifo within a dpram bank by providing just the read address with- out a valid read enable. a fifo empty ?g is generated by the read control logic to the fpga. this empty ?g can be programmed to indicate truly empty or < 1/4 full (1/4 full - 1). lattice semiconductor orca orspi4 data sheet 13 1036-pin ftsbga devices have been discontinued. in addition to formatting received data and sending it to the fpga logic, the receive block also sends status infor- mation to the spi4 status interface. the port status sequencer (pss) block is responsible for providing port status to the spi4 receive status block logic according to a pre-con?ured calendar sequence. status is derived from the ?l-levels of the dpram fifos and/or from the fpga status interface. the spi4 receive status block is responsible for fifo status encoding, calendar management, status pattern encoding (sync bits ?1?, dip-2 calculation and optional calendar selection word encoding. the spi4 receive status block contains the low speed lvttl output buffers and lvds output buffers necessary for the output stage of receive status logic. the option to choose between lvttl or lvds outputs is done by set- ting a control register bit. spi4 debugging and statistics gathering support there are also several other features, including three loopback modes incorporated into the embedded core to assist in debugging and statistic gathering. these features involve both the transmit and receive paths. the three forms of loopback supported directly are: high-speed near-end loopback far-end high-speed loopback low-speed near-end loopback the spi4 blocks support the following error insertion and status reporting options for testing: dip-4 odd parity is calculated over data and control words and inserted on the tx side. dip-4 errors can be forced by inverting the dip-4 parity bits. dip-4 parity is then checked at the receive interface. dip-2 odd parity is calculated over the status frames and inserted on the rx side. dip-2 errors can be forced by inverting the dip-2 parity bits. dip-2 parity is then checked at the transmit status interface. eight-bit counters are provided for counting dip-4 and dip-2 errors. deskew error reporting for high-speed rx side dynamic alignment. this can cause an alarm. dpram fifo overrun reporting. these can cause an alarm. lattice semiconductor orca orspi4 data sheet 14 1036-pin ftsbga devices have been discontinued. memory controller - overview the memory controller block controls an interface to external quad data rate (qdrii) sram for data buffering between the fpga logic and external memory. the key features of the memory controller interface are described below: memory controller features independent memory controller interface to external quad data rate (qdrii) srams from multiple suppliers for data buffering. provides additional packet buffering for > 32 ports provides traf? smoothing for any number of ports the controller supports a throughput of greater than 20 gbits/s so that all the data received on the spi4 inter- face at 10 gbits/s can be buffered. the qdrii sram supports this throughput with 36 unidirectional data lines in both the read and write directions. the controller block provides the ability to access external qdrii sram through the fpga. a set of 72 data signals across the core-fpga interface of the 72, 8 signals can be either used for parity or data. simple asynchronous fifo interface to fpga for ease of design. a high-speed clock signal is provided to the fpga as an option to make the write and read synchronous, if desired. the core passes the data transparently to and from the qdrii sram in two-word or four-word bursts. interfaces to memory are 36 bits wide and the address buses are 18 bits wide. supports the interfaces required for a 512k x 36 bit (18 mbit) qdrii sram in two-word burst mode. only 17 address lines are required in four-word burst mode. status/alarm reported to user through registers data length mismatch from the write controller state machine data instruction coherency error write data, read data fifo overrun and underrun errors additional high-speed memory controller can be implemented in fpga gates if required. serdes logic block - overview the serdes logic block in of the orspi4 contains four clock and data recovery (cdr) macrocells and four seri- alizer/deserializer (serdes) macrocells to support four channels of 8b/10b ( ieee 802.3.2002) encoded serial links. the logic block also contains fiber channel and xaui-based state machines, logic to support multi-channel alignment and mux/demux logic for the fpga/core interface. figure 4 shows the serdes top level block dia- gram and the basic data ?w. boundary scan for the serdes only includes programmable i/os and does not include any of the embedded block i/os. lattice semiconductor orca orspi4 data sheet 15 1036-pin ftsbga devices have been discontinued. figure 4. serdes top level block diagram. the serial channels can each operate at up to 3.7 gbits/s (2.96 gbits/s data rate) with a full-duplex synchronous interface with built-in clock recovery (cdr). the 8b/10b encoding provides guaranteed ones density for the cdr, byte alignment, and error detection. the core is also capable of frame synchronization and physical link monitoring. an overview of the individual blocks in the embedded core is presented in the following paragraphs. the serdes portion of the core contains a quad transceiver block for serial data transmission at a selectable data rate of 0.6 to 3.7 gbits/s. each serdes channel features high-speed 8b/10b parallel i/o interfaces to other core blocks and high-speed cml interfaces to the serial links. serializer and deserializer (serdes) the serdes portion of the core contains a transceiver block for serial data transmission at a selectable data rate of 0.6-3.7 gbits/s. each serdes channel features high-speed 8b/10b parallel i/o interfaces to other core blocks and high-speed cml interfaces to the serial links. the serdes circuitry consists of receiver, transmitter, and auxiliary functional blocks. the receiver accepts high- speed (up to 3.7 gbits/s) serial data. based on data transitions, the receiver locks an analog receive pll for each channel to retime the data, then demultiplexes the data down to parallel bytes and an accompanying clock. the transmitter operates in the reverse direction. parallel bytes are multiplexed up to 3.7 gbits/s serial data for off- chip communication. the transmitter generates the necessary clocks from a lower speed reference clock. the transceiver is controlled and con?ured through the system bus in the fpga logic and through the external 8- bit microprocessor interface of the fpga. each channel has associated dedicated registers that are readable and writable. there are also global registers for control of common circuitry and functions. the serdes performs 8b/10b encoding and decoding for each channel. the 8b/10b transmission code can sup- port either ethernet or fibre channel speci?ations for serial encoding/decoding, special characters, and error detection. the user can disable the 8b/10b decoder to receive raw 10-bit words, which will be rate reduced by the serdes. if this mode is chosen, the user must also bypass the multichannel alignment fifos. the serdes macrocell contains its own dedicated plls for both transmit and receive clock generation. the user provides a reference clock of the appropriate frequency. the receiver plls extract the clock from the serial input data and re-time the data with the recovered clock. mux/demux block the mux/demux logic converts the data format for the high-speed serial links to a wide, low-speed format for crossing the core/fpga interface. the intermediate interface to the serdes macrocell runs at 1/10th the bit serdes w/ clock/data byte- wide data 8b/10b decoder/encoder 4 full- 0.6 gbits/s data duplex serial channels to 3.7 gbits/s 0.6 gbits/s data to 3.7 gbits/s cml i/os orca series 4 fpga logic standard fpga i/os 4:1 mux/1:4 demux recovery lattice semiconductor orca orspi4 data sheet 16 1036-pin ftsbga devices have been discontinued. rate of the data lane. the mux/demux converts the data rate and bus width so the interface to the fpga core can run at 1/4th this intermediate frequency, giving a range of 25.0 to 92.5 mhz for the data rates into and out of the fpga logic. multi-channel alignment fifos in the orspi4 serdes block, the four incoming data channels can be independent of each other or can be syn- chronized in several ways. two channels within a serdes block can be aligned together; channels a and b and/or channels c and d. finally, four channels in a serdes block can be aligned together to form a communication channel with a bandwidth of 10 gbits/s. individual channels within an alignment group can be disabled (i.e., pow- ered down) without disrupting other channels. xaui and fibre channel link state machines two separate link state machines are included in the architecture. a xaui-based link state machine is included in the embedded core to implement the ieee 802.3ae standard. a separate state machine for fibre channel is also implemented. fpga/embedded core interface in 8b/10b mode, the fpga logic will receive/transmit 32-bits of data (up to 92.5 mhz) and four k_ctrl bits from/to the embedded core. there are 4 data streams in each direction plus additional timing, status and control signals. data sent to the fpga can be aligned using comma (/k/) characters or /a/ character as speci?d either by fibre channel or by ieee 802.3ae for xaui based interfaces. the alignment character is made available to the fpga along with the data. the special characters k28.1, k28.5 and k28.7 are treated as valid comma characters by the serdes. if the receive channel alignment fifos are bypassed, then each channel will provide its own receive clock in addi- tion to data and comma character detect signals. if the 8b/10b decoders are bypassed, then 40-bit data streams are passed to the fpga logic. no channel alignment can be done in 8b/10b bypass mode. serdes features four channels of 0.6-3.7g serdes with 8b/10b encoding/decoding are supported. the serdes quad is ieee p802.3ae/d4.01 xaui based and also supports the fc (ansi x3.230:1994) link synchronization state machine speci?ation. the high-speed serdes are programmable and support serial data rates including 622 mbits/s, 1.0 gbits/s, 1.25 gbits/s, 2.5 gbits/s, 3.125 gbits/s, and 3.7 gbits/s. operation has been demonstrated on design tolerance devices at 3.7 gbits/s across 26 in. of fr-4 backplane and at 3.2 gbits/s across 40 in. of fr-4 backplane across temperature and voltage speci?ations. asynchronous operation per receive channel, with the receiver frequency tolerance based on one reference clock per four channels (separate pll per channel). ability to select full-rate or half-rate operation per transmit or receive channel by setting the appropriate control registers. programmable one-half amplitude transmit mode for reduced power in chip-to-chip application. transmit preemphasis (programmable) for improved receive data eye opening. 32-bit (8b/10b) or 40-bit (raw data) parallel internal bus for data processing in fpga logic. provides a 10 gbits/s backplane interface to a switch fabric using four 2.5 gbit/s links. also supports port cards at 2.5 gbit/s. 3.125 gbits/s serdes compliant with xaui serial data speci?ation for 10 gigabit ethernet applications. most xaui features for 10 gigabit ethernet are embedded including the required link state machine. compliant to fibre channel physical layer speci?ation. lattice semiconductor orca orspi4 data sheet 17 1036-pin ftsbga devices have been discontinued. high-speed interface (hsi) function for clock/data recovery serial backplane data transfer without external clocks. four-channel hsi functions provide 2.96 gbits/s serial user data interface per channel (8b/10b encoding and decoding) for a total chip bandwidth of > 10 gbits/s (full duplex). serdes have low-power cml buffers and support 1.5 v or 1.8 v i/os. this allows use of the serdes with opti- cal transceiver, coaxial copper media, shielded twisted pair wiring or high-speed backplanes such as fr-4. powerdown option of serdes hsi receiver or transmitter is on a per-channel basis. automatic lock to reference clock in the absence of valid receive data. high-speed and low-speed loopback test modes. no external components required for clock recovery and frequency synthesis. built-in boundary scan ( ieee 1149.1 and 1149.2 jtag) for the programmable i/os, not including the serdes interface. fifos can align incoming data either across groups of four channels or groups of two channels. alignment is done either using comma characters or by using the /a/ character in xaui mode. optional ability to bypass the alignment fifos for asynchronous operation between channels (each channel includes its own clock and frame pulse or comma detect). orspi4 fpga logic overview the following sections provide a brief overview of the main architectural features of the orspi4 fpga logic. for more detailed information, please refer to the orca series 4 fpga data sheet which can be found under the ?roducts folder on the lattice semiconductor main web site: www.latticesemi.com. the orca series 4 fpga data sheet provides detailed information required for designing with the orspi4 device. topics covered in the orca series 4 data sheet include: fpga logic architecture fpga routing resources fpga clock routing resources fpga programmable input/output cells (pics) fpga embedded block ram (ebr) microprocessor interface (mpi) phase-locked loops (plls) electrical characteristics fpga timing characteristics power-up con?uration orca series 4 fpga logic overview the orca series 4 architecture is a new generation of sram-based programmable devices from lattice. it includes enhancements and innovations geared toward today s high-speed systems on a single chip. designed with networking applications in mind, the series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. orca series 4 devices contain many new patented enhance- ments and are offered in a variety of packages and speed grades. lattice semiconductor orca orspi4 data sheet 18 1036-pin ftsbga devices have been discontinued. the hierarchical architecture of the logic, clocks, routing, ram, and system-level blocks create a seamless merge of fpga and asic designs. modular hardware and software technologies enable system-on-chip integration with true plug-and-play design implementation. the architecture consists of the following basic elements: programmable logic cells (plcs), programmable i/o cells (pios), embedded block rams (ebrs), plus supporting system-level features. these elements are intercon- nected with a rich routing fabric of both global and local wires. an array of plcs is surrounded by common inter- face blocks that provide an abundant interface to the adjacent plcs or system blocks. routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. each plc contains a programmable function unit (pfu), supplemental logic interconnect cell (slic), local rout- ing resources, and con?uration ram. most of the fpga logic is performed in the pfu, but decoders, pa l -like functions, and 3-state buffering can be performed in the slic. the pios provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, uplink and downlink functions, and other functions on two output signals. large blocks of 512 x 18 quad-port ram complement the existing distributed pfu memory. the ram blocks can be used to implement ram, rom, fifo, multiplier, and cam. some of the other system-level functions include the mpi, plls, and the embedded system bus (esb). lattice semiconductor orca orspi4 data sheet 19 1036-pin ftsbga devices have been discontinued. programmable logic features high-performance programmable logic: 0.16 ?, 7-level metal technology. internal performance of >250 mhz. over 600k usable system gates. meets multiple i/o interface standards. 1.5 v operation (30% less power than 1.8 v operation), translates to greater performance. traditional i/o selections: lvttl (3.3v) and lvcmos (2.5 v and 1.8 v) i/os. per pin-selectable i/o clamping diodes provide 3.3 v pci compliance. individually programmable drive capability: 24 ma sink/12 ma source, 12 ma sink/6 ma source, or 6 ma sink/3 ma source. two slew rates supported (fast and slew-limited). fast-capture input latch and input flip-flop (ff)/latch for reduced input setup time and zero hold time. fast open-drain drive capability. capability to register 3-state enable signal. off-chip clock drive capability. two-input function generator in output path. new programmable high-speed i/o: single-ended: gtl, gtl+, pecl, sstl3/2 (class i and ii), hstl (class i, iii, iv), zbt, and ddr. double-ended: lvds, bused-lvds, and lvpecl. programmable, (on/off) internal parallel termination (100 ) is also supported for these i/os. ?ew capability to (de)multiplex i/o signals: new ddr on both input and output at rates up to 350 mhz (700 mbits/s effective rate). new 2x and 4x downlink and uplink capability per i/o (i.e., 50 mhz internal to 200 mhz i/o). enhanced twin-quad programmable function unit (pfu): eight 16-bit look-up tables (luts) per pfu. nine user registers per pfu, one following each lut, and organized to allow two nibbles to act indepen- dently, plus one extra for arithmetic operations. new register control in each pfu has two independent programmable clocks, clock enables, local set/reset, and data selects. new lut structure allows ?xible combinations of lut4, lut5, new lut6, 4 1 mux, new 8 1 mux, and ripple mode arithmetic functions in the same pfu. 32 x 4 ram per pfu, con?urable as single- or dual-port. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the supplemental logic and interconnect cell (slic) decoders as bank drivers. soft-wired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu through fast internal routing which reduces routing congestion and improves speed. flexible fast access to pfu inputs from routing. fast-carry logic and routing to all four adjacent pfus for nibble-wide, byte-wide, or longer arithmetic func- tions, with the option to register the pfu carry-out. abundant high-speed buffered and non-buffered routing resources provide 2x average speed improvements over previous architectures. hierarchical routing optimized for both local and global routing with dedicated routing resources. this results in faster routing times with predictable and ef?ient performance. slic provides eight 3-state buffers, up to a 10-bit decoder, and pa l -like and-or-invert (aoi) in each pro- grammable logic cell. new 200 mhz embedded quad-port ram blocks, 2 read ports, 2 write ports, and 2 sets of byte lane enables. each embedded ram block can be con?ured as: 1?12 x 18 (quad-port, two read/two write) with optional built in arbitration. lattice semiconductor orca orspi4 data sheet 20 1036-pin ftsbga devices have been discontinued. 1?56 x 36 (dual-port, one read/one write). 1?k x 9 (dual-port, one read/one write). 2?12 x 9 (dual-port, one read/one write for each). 2 rams with an arbitrary number of words whose sum is 512 (or less) x 18 (dual-port, one read/one write). supports joining of ram blocks. two 16 x 8-bit content addressable memory (cam) support. fifo 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9. constant multiply (8 x 16 or 16 x 8). dual variable multiply (8 x 8). embedded 32-bit internal system bus plus 4-bit parity interconnects fpga logic, microprocessor interface (mpi), embedded ram blocks, and embedded standard cell blocks with 100 mhz bus performance. included are built- in system registers that act as the control and status center for the device. built-in testability: full boundary scan ( ieee 1149.1 and draft 1149.2 jtag). programming and readback through boundary scan port compliant to ieee draft 1532:d1.7. ts_all testability function to 3-state all i/o pins. new temperature-sensing diode. improved built-in clock management with programmable phase-locked loops (pplls) provide optimum clock modi?ation and conditioning for phase, frequency, and duty cycle from 20 mhz up to 420 mhz. multiplication of the input frequency up to 64x and division of the input frequency down to 1/64x possible. new cycle stealing capability allows a typical 15% to 40% internal speed improvement after ?al place and route. this feature also enables compliance with many setup/hold and clock to out i/o speci?ations and may provide reduced ground bounce for output buses by allowing ?xible delays of switching output buffers. programmable logic system features pci local bus compliant for fpga i/os. improved powerpc ? 860 and powerpc ii high-speed synchronous microprocessor interface can be used for con?uration, readback, device control, and device status, as well as for a general-purpose interface to the fpga logic, rams, and embedded standard cell blocks. glueless interface to synchronous powerpc processors with user-con?urable address space provided. new embedded amba speci?ation 2.0 ahb system bus ( arm processor) facilitates communication among the microprocessor interface, con?uration logic, embedded block ram, fpga logic, and embedded standard cell blocks. variable size bused readback of con?uration data capability with the built-in microprocessor interface and sys- tem bus. internal, 3-state, and bidirectional buses with simple control provided by the slic. new clock routing structures for global and local clocking signi?antly increases speed and reduces skew (<200 ps for or4e04). new local clock routing structures allow creation of localized clock trees. two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved setup/hold and clock to out performance. new double-data rate (ddr) and zero-bus turn-around (zbt) memory interfaces support the latest high- speed memory interfaces. new 2x/4x uplink and downlink i/o capabilities interface high-speed external i/os to reduced speed internal logic. meets universal test and operations phy interface for atm (utopia) levels 1, 2, and 3; as well as pos-phy3. lattice semiconductor orca orspi4 data sheet 21 1036-pin ftsbga devices have been discontinued. plc logic each pfu within a plc contains eight 4-input (16-bit) luts, eight latches/ffs, and one additional flip-flop that may be used independently or with arithmetic functions. the pfu is organized in a twin-quad fashion; two sets of four luts and ffs that can be controlled independently. each pfu has two independent programmable clocks, clock enables, local set/reset, and data selects. luts may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be con?ured as a synchronous 32 x 4 single- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset. the slic is connected from plc routing resources and from the outputs of the pfu. it contains eight 3-state, bidi- rectional buffers, and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert to perform pa l -like functions. the 3-state drivers in the slic and their direct connections from the pfu outputs make fast, true, 3-state buses possible within the fpga, reducing required routing and allowing for real- world system performance. programmable i/o the series 4 pio addresses the demand for the ?xibility to select i/os that meet system interface requirements. i/os can be programmed in the same manner as in previous orca devices, with the additional new features which allow the user the ?xibility to select new i/o types that support high-speed interfaces. each pio contains four programmable i/o pads and is interfaced through a common interface block to the fpga array. the pio is split into two pairs of i/o pads with each pair having independent clock enables, local set/reset, and global set/reset. on the input side, each pio contains a programmable latch/flip-flop, which enables very fast latching of data from any pad. the combination provides for very low setup requirements and zero hold times for signals coming on-chip. it may also be used to demultiplex an input signal, such as a multiplexed address/data sig- nal, and register the signals without explicitly building a demultiplexer with a pfu. on the output side of each pio, an output from the plc array can be routed to each output flip-flop, and logic can be associated with each i/o pad. the output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals. the output ff, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the output buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. in addition, this 3- state signal can be registered or nonregistered. the series 4 i/o logic has been enhanced to include modes for speed uplink and downlink capabilities. these modes are supported through shift register logic, which divides down incoming data rates, or multiplies up outgoing data rates. this new logic block also supports high-speed ddr mode requirements where data is clocked into and out of the i/o buffers on both edges of the clock. the new programmable i/o cell allows designers to select i/os which meet many new communication standards permitting the device to hook up directly without any external interface translation. they support traditional fpga standards as well as high-speed, single-ended, and differential-pair signaling. based on a programmable, bank-ori- ented i/o ring architecture, designs can be implemented using 3.3 v, 2.5 v, 1.8 v, and 1.5 v referenced output lev- els. routing the abundant routing resources of the series 4 architecture are organized to route signals individually or as buses with related control signals. both local and global signals utilize high-speed buffered and non-buffered routes. one plc segmented (x1), six plc segmented (x6), and bused half chip (xhl) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. lattice semiconductor orca orspi4 data sheet 22 1036-pin ftsbga devices have been discontinued. eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be sourced from dedicated i/o pads, plls, or the plc logic. secondary and edge-clock routing is available for fast regional clock or control signal routing for both internal regions and on device edges. secondary clock routing can be sourced from any i/o pin, plls, or the plc logic. the improved routing resources offer great ?xibility in moving signals to and from the logic core. this ?xibility translates into an improved capability to route designs at the required speeds when the i/o signals have been locked to speci? pins. system-level features the series 4 also provides system-level functionality by means of its microprocessor interface, embedded system bus, quad-port embedded block rams, universal programmable phase-locked loops, and the addition of highly tuned networking speci? phase-locked loops. these functional blocks allow for easy, glueless system interfacing and the capability to adjust to varying conditions in today s high-speed networking systems. microprocessor interface the mpi provides a glueless interface between the fpga and powerpc microprocessors. programmable in 8-bit, 16-bit , and 32-bit interfaces with optional parity to the motorola powerpc 860 bus, it can be used for con?uration and readback, as well as for fpga control and monitoring of fpga status. all mpi transactions utilize the series 4 embedded system bus at 66 mhz performance. a system-level microprocessor interface to the fpga user-de?ed logic following con?uration, through the system bus, including access to the embedded block ram and general user-logic, is provided by the mpi. the mpi sup- ports burst data read and write transfers, allowing short, uneven transmission of data through the interface by including data fifos. transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2 bytes), or 16-beat (16 x 1 bytes). system bus an on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the mpi, con?uration logic, fpga control, and status registers, embedded block rams, as well as user logic. utilizing the amba speci- ?ation rev 2.0 ahb protocol, the embedded system bus offers arbiter, decoder, master, and slave elements. master and slave elements are also available for the user-logic and a slave interface is used for control and status of the embedded backplane transceiver portion of the orspi4. the system bus control registers can provide control to the fpga such as signaling for reprogramming, reset func- tions, and pll programming. status registers monitor init, done, and system bus errors. an interrupt controller is integrated to provide up to eight possible interrupt resources. bus clock generation can be sourced from the micro- processor interface clock, con?uration clock (for slave con?uration modes), internal oscillator, user clock from routing, or from the port clock (for jtag con?uration modes). phase-locked loops the orspi4 provides 4 programmable plls accessible through clock routing in the fpga array. there are two standard programmable plls (ppll) and 2 high-speed programmable plls (hppll) available in the orspi4. the two pplls are capable of manipulating and conditioning clock outputs from 15 mhz to 200 mhz. the two hpplls are capable of manipulating and conditioning clock outputs from 60 mhz to 420 mhz. programmable plls can be used to manipulate the frequency, phase, and duty cycle of a clock signal. frequencies can be adjusted from 1/8x to 8x, the input clock frequency. each programmable pll provides two outputs that have differ- ent multiplication factors but can have the same phase relationships. duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. an automatic input buffer delay compensation mode is available for phase delay. each ppll provides two outputs that can have programmable (12.5% steps) phase differences. fpga con?uration the fpga functionality is determined by internal con?uration ram. the fpgas internal initialization/con?uration circuitry loads the con?uration data at power-up or under system control. the con?uration data can reside exter- lattice semiconductor orca orspi4 data sheet 23 1036-pin ftsbga devices have been discontinued. nally in an eeprom or any other storage media. serial eeproms provide a simple, low pin-count method for con- ?uring fpgas. the ram is loaded by using one of several con?uration modes. supporting the traditional master/slave serial, master/slave parallel, and asynchronous peripheral modes, the series 4 also utilizes its microprocessor interface and embedded system bus to perform both programming and readback. daisy chaining of multiple devices and partial recon?uration are also permitted. other con?uration options include the initialization of the embedded-block ram memories and fpsc memory, as well as system bus options and bit stream error checking. programming and readback through the jtag (ieee 1149.2 ) port is also available, meeting in-system programming (isp) standards ( ieee 1532 draft). fpsc con?uration con?uration of the orspi4 occurs in two stages: fpga bit-stream con?uration and embedded core setup. prior to becoming operational, the fpga goes through a sequence of states, including power-up, initialization, con- ?uration, start-up, and operation. the fpga logic is con?ured by standard fpga bit-stream con?uration means as discussed in the orca series 4 fpga data sheet. after the fpga con?uration is complete, the options for the embedded core are set based on the contents of reg- isters that are accessed through the fpga system bus. the system bus itself can be driven by an external pow- erpc compliant microprocessor via the mpi block or via a user master interface in fpga logic. a simple ip block that drives the system by using the user register interface and very little fpga logic is available in the mpi/system bus technical note (tn-1017) . this ip block sets up the embedded core via a state machine and allows the orspi4 to work in an independent system without an external microprocessor interface. orspi4 package options the orspi4 fpsc is available in two package options: a 1036 ftsbga and a 1156 fpbga. the 1036 pin package provides an or4e06 fpga array (16,192 les, 148 kbits of embedded block ram), 498 fpga user i/os, two spi4 interfaces (or one spi4 interface and a quad high-speed serdes interface), and a high-speed qdrii sram controller. the 1156 pin package provides an or4e06 fpga array (16,192 les, 148 kbits of embedded block ram), 356 fpga user i/os, two spi4 interfaces (serdes interface not available on this package), and a high- speed qdrii sram controller. additional information contact your local lattice representative for additional information regarding the orca series 4 fpga devices, or visit our website at: http://www.latticesemi.com/orca links to specs and standards optical internetworking forum ?oif-spi4-02.0 - www .oif or um.com fibre channel physical and signaling interface ?fc-ph ansi x3.230-1994 - www .t11.org 10 gigabit ethernet ?ieee p802.3ae - www .ieee .org 18mb qdr-ii sram 2-word burst ?mt54w512h36b - www .cypress .com/products/micron/micron.cfm 18mb qdr-ii sram 4-word burst ?mt54w512h36b - www .cypress .com/products/micron/micron.cfm 36mb qdr-ii sram 2-word burst ?ktr323682m - www .samsung.com/products/semiconductor/sram/inde x.htm 36mb qdr-ii sram 4-word burst ?ktr323684m - www .samsung.com/products/semiconductor/sram/inde x.htm lattice semiconductor orca orspi4 data sheet 24 1036-pin ftsbga devices have been discontinued. orspi4 spi4 data formats the data format across the spi4 interface follows the oif spi4 convention where the lowest byte number occupies the highest bit positions within the 16-bit word as shown in figure 5. on payload transfers that do not end on an even byte boundary, the unused byte (after the last valid byte) on bit positions 7 through 0 is set to all zeroes as shown in figure 5. figure 5. spi4 byte and bit ordering at the fpga-embedded core rx and tx interface, the same spi4 convention is followed wherein the lowest byte number occupies the highest bit positions within a word. this is the same in all operating modes - 32-bit, 64-bit and 128-bit. byte enables for all data except eop should be ?? during an eop, the last valid byte enable within a 32-bit, 64-bit or 128-bit word indicates the last byte for the packet. figure 6 shows eop signal being asserted during word 3. in figure 6, the last valid byte enable within ?110 in word 3 indicates the eop. the valid byte enables during an eop are ?111? ?110? ?100 and ?000? if the packet was errored, the err signal is asserted and will remain asserted until eop as shown in figure 6 figure 6. example of eop indication in 32-bit mode byte 0 byte 1 15 7 0 byte 2 byte 3 byte 4 x (set to zeros) byte 0 byte 1 15 7 0 byte 2 byte 3 byte 4 x (set to zeros) tdat rdat word 0 word 1 word 2 word 3 0123 012 3 0123 0123 1 byte bit be0 be1 be2 be3 11 1 1 111 11 1 1 11 1 0 spi[a,b]_tx32_eop_j clock 1 clock 2 clock 3 clock 4 spi[a,b]_tx32_err_j spi[a,b]_rx32_eop_j spi[a,b]_rx32_err_j lattice semiconductor orca orspi4 data sheet 25 1036-pin ftsbga devices have been discontinued. the bit ordering in the data format in the 32-bit aggregation mode is shown in figure 7. in 32-bit mode, data trans- fers are done in 4-word bursts with the exception of an eop. as shown in the ?ure, sop is always aligned to the most signi?ant 32-bit word, word 0 of a 4-word burst. the ?st byte of a packet is always word 0. the sop indica- tor is high during word 0. eop can be any byte within the 32-bit word. the last valid byte enable within a 32-bit word indicates the end of packet. the eop signal can be high during word 0, word 1, word 2 or word 3. it should be used in conjunction with the byte enables to determine the last byte in that data transfer. if data transfers do not end on word 3, then the burst is terminated and word 0 of the next burst is sent to the user. for example, if eop occurs during word 2, word 3 will be discarded and word 0 of the next word will be sent to the user. figure 7. byte and bit ordering in 32-bit operating mode the bit ordering in the data format in the 64-bit aggregation mode is shown in figure 8. in 64-bit mode, data trans- fers are done in 2-word bursts with the exception of an eop. as shown in the ?ure, sop is always aligned to the most signi?ant 64-bit word 0 of a 2-word burst. the ?st byte of a packet is always word 0. the sop indicator is high during word word 0. figure 8. byte and bit ordering in 64-bit mode 31 23 15 7 0 byte 0 byte 1 byte 2 byte 3 31 23 15 7 0 byte 0 byte 1byte 2 byte 3 31 23 15 7 0 byte 0 byte 1 byte 2 byte 3 31 23 15 7 0 byte 0 byte 1byte 2 byte 3 word 3 spi[a,b]_rx32_data_j[31:0] clock 1 clock 2 clock 3 clock 4 word 2 word 1 word 0 spi[a,b]_rx32_sop_j 127 0 95 63 31 dpram fpga w 0 w 2 w 3 w 1 time byte 0 is the sop spi[a,b]_tx32_data_j[31:0] or spi[a,b]_rx32_sop_j 31 23 15 7 0 byte4 byte 5byte 6 byte 7 63 55 47 39 32 byte 0 byte 1byte 2 byte 3 31 23 15 7 0 byte 4byte 5byte 6 byte 7 63 55 47 39 32 byte 0 byte 1byte 2 byte 3 clock 1 clock 2 word 1 word 0 spi[a,b]_rx64_sop_j 127 0 95 63 31 dpram fpga word 1 word 0 time spi[a,b]_rx64_data_j[63:0] spi[a,b]_tx64_data_j[63:0] or spi[a,b]_tx64_sop_j lattice semiconductor orca orspi4 data sheet 26 1036-pin ftsbga devices have been discontinued. the bit ordering in the data format in the 128-bit aggregation mode is shown in figure 9. the ?st byte of a packet is always byte 0 of the 128-bit word. as shown in the ?ure, sop is always aligned to the most signi?ant 64-bit word 0 of a 2-word burst. sop is always aligned to byte 0 of the 128-bit word. figure 9. byte and bit ordering in 128-bit mode 31 23 15 7 0 byte12 byte 13 byte 14 byte 15 63 55 47 39 32 byte 8 byte 9 byte 10 byte 11 95 87 79 71 64 byte 4 byte 5 byte 6 byte 7 127 119 111 103 96 byte 0 byte 1 byte 2 byte 3 clock 1 word 0 spi[a,b]_rx128_sop 127 0 95 63 31 dpram fpga word 0 time spi[a,b]_rx128_data[127:0] spi[a,b]_tx128_data[127:0] or spi[a,b]_tx128_sop lattice semiconductor orca orspi4 data sheet 27 1036-pin ftsbga devices have been discontinued. spi4 transmit path functional description this section describes the transmit section of the spi4 interface. the orspi4 device contains two identical, yet independent transmit spi4 compliant interfaces within the fpsc. the description provided within this section is applicable to both transmit spi4 interfaces. the transmit spi4 interface supports the following features: independent tx interface that is not tied to associated receive spi4 interface 10 gbit/s data throughput 4 dual-port memories used to provide 256 bytes of buffering for up to 32 ports. if support for more than 32 ports is required, the dual-port memories can be used, or they can be used for clock crossing purposes while data is buffered with external memory. simple fifo-like interface from fpga to spi4 tx embedded core block. calendar control logic, including the transmit calendar, shadow calendar and support for up to 256 ports (the maximum allowable number of spi4 ports). mixed data width aggregation modes at the user transmit interface. 32, 64, and 128-bit modes are supported. programmable calendar table, supporting all calendar con?uration parameters as speci?d in the spi4 stan- dard. feedback to fpga of currently serviced spi4 port. the transmit spi4 logic enables users to write port data from a variety of interfaces and associated clock domains using dual port rams (dpram) for temporary storage and clock domain crossing. data is written into the dpram banks from the fpga and read according to a pre-con?ured transmit calendar sequence. data is formatted into the spi4 format and transmitted to the physical links as lvds signals, as speci?d by oif-spi4-02.0. in addition to the transmit data path, out-of-band status information is received on the transmit status lines. this information is used, along with precon?ured calendar sequence information, to schedule the servicing of spi4 port for data transmission. the status information is also passed back to the fpga logic. there are also several other features incorporated into the embedded core such as parallel loopback and spi4 loopback to assist in debugging and statistic gathering. the major blocks associated with the orspi4 transmitter are: four transmit dpram banks address map and arbiter (ama) transmit calendar control logic port write sequencer logic (pws) spi4 logic - data spi4 transmit data logic (tdp) spi4 transmit i/o interface (tdo) spi4 transmit status logic (tsp) spi4 transmit status interface (tsi) spi4 transmit status protocol (tsp) these blocks will be described in detail in the following sections. the orspi4 transmit functional block diagram is shown in figure 10. . lattice semiconductor orca orspi4 data sheet 28 1036-pin ftsbga devices have been discontinued. figure 10. orspi4 transmit functional block diagram orspi4 transmit functional block overview the user can write transmit data and associated control signals to the tx dpram bank using either multiple 32- or 64-bit interfaces, or a single aggregated 128-bit interface. the data bus interface is software con?urable. the tx dpram block is made up of 4 con?urable dprams, used for transmit data buffering and clock domain crossing. the dprams can be con?ured via software to support up to 8 virtual partitions each, providing a maximum of 32 virtual fifos, each being 256 bytes deep. data is read from the dprams according to the con?ured transmit calendar within the tx calendar control logic. the control logic provides both the virtual partition address and burst_val to the address map & arbiter (ama) block. the ama services the requested partition and can option- ally provide idle data if the partition is empty when serviced. the tdp block accepts transmit data and control sig- nals from the ama and formats the data according to the spi4 transmit data protocol. the transmit data is then serialized within the tdo block. data is transmitted across the spi4 interface on a 16-bit lvds pair bus (tdat) which is source synchronous to the lvds pair clock (tdclk). the lvds control signal pair (tctl) is used to iden- tify when the content of the spi4 bus is control versus user data. the interface is an oif-spi-4 02.0 compliant interface that supports data rates in the range of 622-900 mbps. additionally, lower speed data in the range of 100- 200 mbps is also supported. to accommodate dynamic timing the tdp will insert training patterns as con?ured. [a,b]tstat [a,b]tsclk tx dpram spi[a,b]_k_data_j, bej spi[a,b]_k_sopj, errj spi[a,b]_k_port_j spi[a,b]_k_wd_cnt_rst_j spi[a,b]_k_we_j tdo [a,b]tdat [a,b]tctl [a,b]tdclk tx calendar tsp tsi spi[a,b]_k_port_id spi[a,b]_k_stat spi[a,b]_k_burst_val tlstat tlclk 8 tdp address map & arbiter tdp k = tx32, tx64 or tx128 spi[a,b]_k_link_dis_j spi[a,b]_k_fifo_full_j spi[a,b]_k_clk_j spi[a,b]_k_port_id control logic fpga interface port_id port_stat 2 4 ama_id burst_val 16 2 spi[a,b]_k_addrj j = 0, 1, 2 or 3 lattice semiconductor orca orspi4 data sheet 29 1036-pin ftsbga devices have been discontinued. far-end status is received by the tsi block and sent to the tsp block for buffering. the interface supports quarter- rate status from either lvds or ttl inputs. the tsp block provides both the port identi?ation and current status to the tx calendar control logic, where internal tables are updated accordingly to provide proper port servicing. orspi4 transmit fpga/embedded core interface description the fpga i/o interface to the orspi4 logic supports several interface features and varying interface characteris- tics, depending upon the con?ured mode of operation. the modes are referred to as 'aggregation modes' due to the nature of the aggregation of data busses for the different modes of operation. there are three data aggregation modes supported by the transmit core: 32-bit mode: each of the 4 dprams can be con?ured to use a 32-bit user data interface plus associated control signals across the fpga interface. this interface is useful when interfacing the spi4 data pipe to one or more sub-rate channels. this mode provides up to 4 independent 32-bit interfaces. in this mode, the interfaces do not need to be synchronous with each other. 64-bit mode: dpram pairs {[0:1], [2:3]} are con?ured to serve as 64-bit user data interfaces, plus associated control signals. note that 32-bit and 64-bit modes can be combined to provide up to 3 independent interfaces. 128-bit mode: all four dpram banks are aggregated into a single fifo with a 128-bit user-data interface from the fpga. to maintain compliance with the spi-4.2 interface protocol, the user is required to burst a minimum of 16 data bytes per write period. this is required for all modes of aggregation. for 32-bit mode, four writes are required, for 64-bit mode, two writes are required. for 128-bit mode, a single write access will provide 16 bytes of data. several other features are: auto-increment of the dpram write address pointer when an eop is detected. prohibit data writes if no associated byte-enable (be) bits are asserted within an entire 128-bit line, optimizing the fifo memory locations by not wasting memory. the ability for the user to disable one or more of the interface links using the spi[a,b]_k_link_dis_j signals. this causes the ama logic to cease polling from a dpram. all ports associated with a disabled dpram will remain unserviced until the control signal is deasserted. the ability for the user to reset a port s write pointer with the spi[a,b]_k_wd_cnt_rst_j signal. this can be used to customize data applications or as a diagnostic test function. the ability for the user to individually poll for dpram fifo ?l status. normal fifo status is provided whenever the user attempts to write data to the dprams. if an address is provided to the fifo without a write enable, fifo status is still provided. this feature is useful when the application requires knowing the status of individual virtual fifos but is not prepared to write data to it. table 2 lists the i/os for the transmit spi4a core only. the interface signals for core b are identical with the names modi?d appropriately. table 3 and table 4 list the i/o for the transmit spi4 core for 64-bit and 128-bit aggregation modes respectively. lattice semiconductor orca orspi4 data sheet 30 1036-pin ftsbga devices have been discontinued. table 2. spia core transmit fpga interface in 32-bit mode dpram fpga interface i/os direction from/to description 0 spia_tx32_addr_0[2:0] fpga core virtual fifo write address. each dpram can be divided up to a maximum of eight partitions. more than one port can be con?ured to share a virtual fifo partition. spia_tx32_data_0[31:0] fpga core user write data. four writes are required in order to complete an entire 128- bit line. all writes must occur in four write bursts, unless an eop occurs. spia_tx32_be_0[3:0] fpga core byte enables indicating which bytes within the 32-bit word are valid. bit[3]-byte enable for spia_tx32_data_0[31:24] bit[2]-byte enable for spia_tx32_data_0[23:16] bit[1]-byte enable for spia_tx32_data_0[15:8] bit[0]-byte enable for spia_tx32_data_0[7:0] if no be bits are asserted for a particular location within the dpram, port data will be dropped and no write to the dpram will occur. according to the spi-4.2 speci?ation, the be bits must be asserted for all but the last transfer, where an end of packet or error may occur. the valid combinations of be are as follows: be[3:0] = 1111--indicates all four bytes contain valid user data be[3:0] = 1110--indicates three bytes are valid. eop occurs in third byte. be[3:0] = 1100--indicates two bytes are valid. eop occurs in second byte. be[3:0] = 1000--indicates one byte is valid. eop occurs in ?st byte. spia_tx32_sop_0 fpga core start of packet indicator. a '1' indicates the start of packet for a particular port. when operating in either 32- or 64-bit mode, the sop indicator must be asserted coincident with the ?st write per address line within the fifo par- tition. spia_tx32_eop_0 fpga core end of packet indicator. a '1' indicates the end of packet for a particular port. the eop may be asserted on any write per address line within the fifo partition. when an eop is detected by the dpram write pointer logic, the address pointer will be automatically incremented to the next location within the fifo partition range. spia_tx32_err_0 fpga core packet error indication. a '1' indicates an error has occurred for the current packet being transmitted. the err signal must be asserted coincident with the eop signal. spia_tx32_we_0 fpga core write enable. a logic '1' causes data on the spia_tx32_data_0[31:0] bus to be captured for a write to the dpram. spia_tx32_port_0[7:0] fpga core spi4 port indicator, used to associate the current transmit data with a par- ticular port number. spia_tx32_wd_cnt_rst_ 0 fpga core line write termination indicator. this signal causes the fifo write address pointer within the embedded core to increment to the next address location for the addressed partition. this signal can be used for custom applications as well as for diagnostic test functions. spia_tx32_link_dis_0 fpga core link disable control signal. when asserted to a logic '1', the ama will cease polling from a dpram. all ports associated with a disabled dpram will remain unserviced until the control signal is deasserted. the ama will send idle data across the spi4 link. if the application continues to write data to that port fifo, it will eventually ?l and provide proper fifo ?l status to the application. spia_tx32_clk_0 fpga core transmit write reference clock. the clocks across the different transmit interfaces are independent from each other, and are not required to be syn- chronous to each other. spia_tx32_fifo_full_0 core fpga fifo full status. the status is given in response to the assertion of any valid address on the spia_tx32_addr_0[2:0] bus. this signal will be asserted to a logic '1' when the current fifo partition has crossed the con- ?ured ?l level within the partition. note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 31 1036-pin ftsbga devices have been discontinued. 1 spia_tx32_addr_1[2:0] fpga core virtual fifo write address. each dpram can be divided up to a maximum of eight partitions. more than one port can be con?ured to share a virtual fifo partition. spia_tx32_data_1[31:0] fpga core user write data. four writes are required in order to complete an entire 128-bit line. all writes must occur in four write bursts, unless an eop occurs. spia_tx32_be_1[3:0] fpga core byte enables indicating which bytes within the 32-bit word are valid. bit[3]-byte enable for spia_tx32_data_0[31:24] bit[2]-byte enable for spia_tx32_data_0[23:16] bit[1]-byte enable for spia_tx32_data_0[15:8] bit[0]-byte enable for spia_tx32_data_0[7:0] if no be bits are asserted for a particular location within the dpram, port data will be dropped and no write to the dpram will occur. according to the spi-4.2 speci?ation, the be bits must be asserted for all but the last transfer, where an end of packet or error may occur. the valid combinations of be are as follows: be[3:0] = 1111--indicates all four bytes contain valid user data be[3:0] = 1110--indicates three bytes are valid. eop occurs in third byte. be[3:0] = 1100--indicates two bytes are valid. eop occurs in second byte. be[3:0] = 1000--indicates one byte is valid. eop occurs in ?st byte. spia_tx32_sop_1 fpga core start of packet indicator. a '1' indicates the start of packet for a particular port. when operating in either 32- or 64-bit mode, the sop indicator must be asserted coincident with the ?st write per address line within the fifo partition. spia_tx32_eop_1 fpga core end of packet indicator. a '1' indicates the end of packet for a particular port. the eop may be asserted on any write per address line within the fifo partition. when an eop is detected by the dpram write pointer logic, the address pointer will be automatically incremented to the next location within the fifo partition range. spia_tx32_err_1 fpga core packet error indication. a '1' indicates an error has occurred for the current packet being transmitted. the err signal must be asserted coincident with the eop signal. spia_tx32_we_1 fpga core write enable. a logic '1' causes data on the spia_tx32_data_1[31:0] bus to be captured for a write to the dpram. spia_tx32_port_1[7:0] fpga core spi4 port indicator, used to associate the current transmit data with a par- ticular port number. spia_tx32_wd_cnt_rst_ 1 fpga core line write termination indicator. this signal causes the fifo write address pointer within the embedded core to increment to the next address location for the addressed partition. this signal can be used for custom applications as well as for diagnostic test functions. spia_tx32_link_dis_1 fpga core link disable control signal. when asserted to a logic '1', the ama will cease polling from a dpram. all ports associated with a disabled dpram will remain unserviced until the control signal is deasserted. the ama will send idle data across the spi4 link. if the application continues to write data to that port fifo, it will eventually ?l and provide proper fifo ?l status to the application. spia_tx32_clk_1 fpga core transmit write reference clock. the clocks across the different transmit interfaces are independent from each other, and are not required to be syn- chronous to each other. spia_tx32_fifo_full_1 core fpga fifo full status. the status is given in response to the assertion of any valid address on the spia_tx32_addr_1[2:0] bus. this signal will be asserted to a logic '1' when the current fifo partition has crossed the con- ?ured ?l level within the partition. table 2. spia core transmit fpga interface in 32-bit mode (continued) dpram fpga interface i/os direction from/to description note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 32 1036-pin ftsbga devices have been discontinued. 2 spia_tx32_addr_2[2:0] fpga core virtual fifo write address. each dpram can be divided up to a maximum of eight partitions. more than one port can be con?ured to share a virtual fifo partition. spia_tx32_data_2[31:0] fpga core user write data. four writes are required in order to complete an entire 128-bit line. all writes must occur in four write bursts, unless an eop occurs. spia_tx32_be_2[3:0] fpga core byte enables indicating which bytes within the 32-bit word are valid. bit[3]-byte enable for spia_tx32_data_0[31:24] bit[2]-byte enable for spia_tx32_data_0[23:16] bit[1]-byte enable for spia_tx32_data_0[15:8] bit[0]-byte enable for spia_tx32_data_0[7:0] if no be bits are asserted for a particular location within the dpram, port data will be dropped and no write to the dpram will occur. according to the spi-4.2 speci?ation, the be bits must be asserted for all but the last transfer, where an end of packet or error may occur. the valid combinations of be are as follows: be[3:0] = 1111--indicates all four bytes contain valid user data. if an eop is present, it resides within the fourth byte. be[3:0] = 1110--indicates three bytes are valid. eop occurs in third byte. be[3:0] = 1100--indicates two bytes are valid. eop occurs in second byte. be[3:0] = 1000--indicates one byte is valid. eop occurs in ?st byte. spia_tx32_sop_2 fpga core start of packet indicator. a '1' indicates the start of packet for a particular port. when operating in either 32- or 64-bit mode, the sop indicator must be asserted coincident with the ?st write per address line within the fifo partition. spia_tx32_eop_2 fpga core end of packet indicator. a '1' indicates the end of packet for a particular port. the eop may be asserted on any write per address line within the fifo partition. when an eop is detected by the dpram write pointer logic, the address pointer will be automatically incremented to the next location within the fifo partition range. spia_tx32_err_2 fpga core packet error indication. a '1' indicates an error has occurred for the current packet being transmitted. the err signal must be asserted coincident with the eop signal. spia_tx32_we_2 fpga core write enable. a logic '1' causes data on the spia_tx32_data_2[31:0] bus to be captured for a write to the dpram. spia_tx32_port_2[7:0] fpga core spi4 port indicator, used to associate the current transmit data with a par- ticular port number. spia_tx32_wd_cnt_rst_ 2 fpga core line write termination indicator. this signal causes the fifo write address pointer within the embedded core to increment to the next address location for the addressed partition. this signal can be used for custom applications as well as for diagnostic test functions. spia_tx32_link_dis_2 fpga core link disable control signal. when asserted to a logic '1', the ama will cease polling from a dpram. all ports associated with a disabled dpram will remain unserviced until the control signal is deasserted. the ama will send idle data across the spi4 link. if the application continues to write data to that port fifo, it will eventually ?l and provide proper fifo ?l status to the application. spia_tx32_clk_2 fpga core transmit write reference clock. the clocks across the different transmit interfaces are independent from each other, and are not required to be syn- chronous to each other. spia_tx32_fifo_full_2 core fpga fifo full status. the status is given in response to the assertion of any valid address on the spia_tx32_addr_3[2:0] bus. this signal will be asserted to a logic '1' when the current fifo partition has crossed the con- ?ured ?l level within the partition. table 2. spia core transmit fpga interface in 32-bit mode (continued) dpram fpga interface i/os direction from/to description note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 33 1036-pin ftsbga devices have been discontinued. 3 spia_tx32_addr_3[2:0] fpga core virtual fifo write address. each dpram can be divided up to a maximum of eight partitions. more than one port can be con?ured to share a virtual fifo partition. spia_tx32_data_3[31:0] fpga core user write data. four writes are required in order to complete an entire 128-bit line. all writes must occur in four write bursts, unless an eop occurs. spia_tx32_be_3[3:0] fpga core byte enables indicating which bytes within the 32-bit word are valid. bit[3]-byte enable for spia_tx32_data_0[31:24] bit[2]-byte enable for spia_tx32_data_0[23:16] bit[1]-byte enable for spia_tx32_data_0[15:8] bit[0]-byte enable for spia_tx32_data_0[7:0] if no be bits are asserted for a particular location within the dpram, port data will be dropped and no write to the dpram will occur. according to the spi-4.2 speci?ation, the be bits must be asserted for all but the last transfer, where an end of packet or error may occur. the valid combinations of be are as follows: be[3:0] = 1111--indicates all four bytes contain valid user data. if an eop is present, it resides within the fourth byte. be[3:0] = 1110--indicates three bytes are valid. eop occurs in third byte. be[3:0] = 1100--indicates two bytes are valid. eop occurs in second byte. be[3:0] = 1000--indicates one byte is valid. eop occurs in ?st byte. spia_tx32_sop_3 fpga core start of packet indicator. a '1' indicates the start of packet for a particular port. when operating in either 32- or 64-bit mode, the sop indicator must be asserted coincident with the ?st write per address line within the fifo partition. spia_tx32_eop_3 fpga core end of packet indicator. a '1' indicates the end of packet for a particular port. the eop may be asserted on any write per address line within the fifo partition. when an eop is detected by the dpram write pointer logic, the address pointer will be automatically incremented to the next location within the fifo partition range. spia_tx32_err_3 fpga core packet error indication. a '1' indicates an error has occurred for the current packet being transmitted. the err signal must be asserted coincident with the eop signal. spia_tx32_we_3 fpga core write enable. a logic '1' causes data on the spia_tx32_data_3[31:0] bus to be captured for a write to the dpram. spia_tx32_port_3[7:0] fpga core spi4 port indicator, used to associate the current transmit data with a par- ticular port number. spia_tx32_wd_cnt_rst_ 3 fpga core line write termination indicator. this signal causes the fifo write address pointer within the embedded core to increment to the next address location for the addressed partition. this signal can be used for custom applications as well as for diagnostic test functions. spia_tx32_link_dis_3 fpga core link disable control signal. when asserted to a logic '1', the ama will cease polling from a dpram. all ports associated with a disabled dpram will remain unserviced until the control signal is deasserted. the ama will send idle data across the spi4 link. if the application continues to write data to that port fifo, it will eventually ?l and provide proper fifo ?l status to the application. spia_tx32_clk_3 fpga core transmit write reference clock. the clocks across the different transmit interfaces are independent from each other, and are not required to be syn- chronous to each other. spia_tx32_fifo_full_3 core fpga fifo full status. the status is given in response to the assertion of any valid address on the spia_tx32_addr_3[2:0] bus. this signal will be asserted to a logic '1' when the current fifo partition has crossed the con- ?ured ?l level within the partition. table 2. spia core transmit fpga interface in 32-bit mode (continued) dpram fpga interface i/os direction from/to description note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 34 1036-pin ftsbga devices have been discontinued. status i/os spia_tx32_port_id[7:0] core fpga port number of the currently serviced spi4 data port. the value can either be the actual spi4 value or a programmed user value. further details are provided in the tx calendar control logic description. spia_tx32_stat[1:0] core fpga status of the spi4 port currently being serviced. these signals can be used in conjunction with the spia_tx32_port_id signal to police trans- mit traf? congestion for a particular spi4 port. spia_tx32_burst_val[3:0] core fpga indicates the number of spi4 cycles for which the currently active port will be serviced. each cycle indicates an attempt to read 128 bits of data from the respective fifo partition. atrefclk_f core fpga transmit reference clock. this clock signal is 1/4th the spi4 clock. this sig- nal can be used to synchronize fpga application logic to the fpsc logic. spia_trefclk_x8 fpga core quarter-rate transmit reference clock. this fpga-sourced clock reference must be 2x the desired transmit spi4 line clock rate. when not operating the transmit spi4 core in quarter-rate mode, this signal should be tied off. ex: for a 100 mhz transmit spi4 line clock, spia_trefclk_x8 from the fpga must be 200 mhz. misc. i/os spi_satm_a fpga core ? - incoming atsclk is assumed to be edge-aligned with the data and centered to the data eye within the chip. ? - incoming atsclk is assumed to be skewed with respect to the data off-chip. table 2. spia core transmit fpga interface in 32-bit mode (continued) dpram fpga interface i/os direction from/to description note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 35 1036-pin ftsbga devices have been discontinued. table 3. spia core transmit fpga interface in 64-bit mode dpram fpga interface i/os direction from/to description 0 spia_tx64_addr_0[2:0] fpga core virtual fifo write address. each dpram can be divided up to a maximum of eight partitions. when operating in 64-bit mode, each partition will be 2x the depth of the corresponding partition in 32-bit mode. more than one port can be con?ured to share a virtual fifo partition. spia_tx64_data_0[63:0] fpga core user write data. two writes are required in order to complete an entire 128- bit line. all writes must occur in two write bursts, unless an eop occurs. spia_tx64_be_0[7:0] fpga core byte enables indicating which bytes within the 64-bit word are valid. bit[7]-byte enable for spia_tx64_data_0[63:56] bit[6]-byte enable for spia_tx64_data_0[55:48] bit[5]-byte enable for spia_tx64_data_0[47:40] bit[4]-byte enable for spia_tx64_data_0[39:32] bit[3]-byte enable for spia_tx64_data_0[31:24] bit[2]-byte enable for spia_tx64_data_0[23:16] bit[1]-byte enable for spia_tx64_data_0[15:8] bit[0]-byte enable for spia_tx64_data_0[7:0] if no be bits are asserted for a particular location within the dpram, data will be dropped and no write to the dpram will occur. according to the spi-4.2 speci?ation, the be bits must be asserted for all but the last transfer, where an end of packet or error may occur. the valid combinations of be are as follows: be[7:0] = 11111111--indicates all eight bytes contain valid user data. if an eop is present, it resides within the eighth byte. be[7:0] = 11111110--indicates seven bytes are valid. eop occurs in seventh byte. be[7:0] = 11111100--indicates six bytes are valid. eop occurs in sixth byte. be[7:0] = 11111000--indicates ve byte is valid. eop occurs in fth byte. be[7:0] = 11110000--indicates four bytes are valid. eop occurs in fourth byte. be[7:0] = 11100000--indicates three bytes are valid. eop occurs in third byte. be[7:0] = 11000000--indicates two bytes are valid. eop occurs in second byte. be[7:0] = 10000000--indicates one byte is valid. eop occurs in rst byte. spia_tx64_sop_0 fpga core start of packet indicator. a '1' indicates the start of packet for a particular port. when operating in 64-bit mode, the sop indicator must be asserted coincident with the ?st write per address line within the fifo partition. spia_tx64_eop_0 fpga core end of packet indicator. a '1' indicates the end of packet for a particular port. the eop may be asserted on either write per address line within the fifo partition. when an eop is detected by the dpram write pointer logic, the address pointer will be automatically incremented to the next location within the fifo partition range. spia_tx64_err_0 fpga core packet error indication. a '1' indicates an error has occurred for the current packet being transmitted. the err signal must be asserted coincident with the eop signal. spia_tx64_we_0 fpga core write enable. a logic '1' causes data on the spia_tx64_data_0[63:0] bus to be captured for a write to the dpram. spia_tx64_port_0[7:0] fpga core spi4 port indicator, used to associate the current transmit data with a par- ticular port number. spia_tx64_wd_cnt_rst_ 0 fpga core line write termination indicator. this signal causes the fifo write address pointer within the embedded core to increment to the next address location for the addressed partition. this signal can be used for custom applications as well as for diagnostic test functions. note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 36 1036-pin ftsbga devices have been discontinued. 0 spia_tx64_link_dis_0 fpga core link disable control signal. when asserted to a logic '1', the ama will cease polling from a dpram. all ports associated with a disabled dpram will remain unserviced until the control signal is deasserted. the ama will send idle data across the spi4 link. if the application continues to write data to that port fifo, it will eventually ?l and provide proper fifo ?l status to the application. spia_tx64_clk_0 fpga core transmit write reference clock. the clocks across the different transmit interfaces are independent from each other, and are not required to be syn- chronous to each other. spia_tx64_fifo_full_0 core fpga fifo full status. the status is given in response to the assertion of any valid address on the spia_tx64_addr_1[2:0] bus. this signal will be asserted to a logic '1' when the current fifo partition has crossed the con- ?ured ?l level within the partition. 1 spia_tx64_addr_1[2:0] fpga core virtual fifo write address. each dpram can be divided up to a maximum of eight partitions. when operating in 64-bit mode, each partition will be 2x the depth of the corresponding partition in 32-bit mode. more than one port can be con?ured to share a virtual fifo partition. spia_tx64_data_1[63:0] fpga core user write data. two writes are required in order to complete an entire 128- bit line. all writes must occur in two write bursts, unless an eop occurs. spia_tx64_be_1[7:0] fpga core byte enables indicating which bytes within the 64-bit word are valid. bit[7]-byte enable for spia_tx64_data_0[63:56] bit[6]-byte enable for spia_tx64_data_0[55:48] bit[5]-byte enable for spia_tx64_data_0[47:40] bit[4]-byte enable for spia_tx64_data_0[39:32] bit[3]-byte enable for spia_tx64_data_0[31:24] bit[2]-byte enable for spia_tx64_data_0[23:16] bit[1]-byte enable for spia_tx64_data_0[15:8] bit[0]-byte enable for spia_tx64_data_0[7:0] if no be bits are asserted for a particular location within the dpram, data will be dropped and no write to the dpram will occur. according to the spi-4.2 speci?ation, the be bits must be asserted for all but the last transfer, where an end of packet or error may occur. the valid combinations of be are as follows: be[7:0] = 11111111--indicates all eight bytes contain valid user data. if an eop is present, it resides within the eighth byte. be[7:0] = 11111110--indicates seven bytes are valid. eop occurs in sev- enth byte. be[7:0] = 11111100--indicates six bytes are valid. eop occurs in sixth byte. be[7:0] = 11111000--indicates ?e byte is valid. eop occurs in ?th byte. be[7:0] = 11110000--indicates four bytes are valid. eop occurs in fourth byte. be[7:0] = 11100000--indicates three bytes are valid. eop occurs in third byte. be[7:0] = 11000000--indicates two bytes are valid. eop occurs in second byte. be[7:0] = 10000000--indicates one byte is valid. eop occurs in ?st byte. spia_tx64_sop_1 fpga core start of packet indicator. a '1' indicates the start of packet for a particular port. when operating in 64-bit mode, the sop indicator must be asserted coincident with the ?st write per address line within the fifo partition. spia_tx64_eop_1 fpga core end of packet indicator. a '1' indicates the end of packet for a particular port. the eop may be asserted on either write per address line within the fifo partition. table 3. spia core transmit fpga interface in 64-bit mode (continued) dpram fpga interface i/os direction from/to description note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 37 1036-pin ftsbga devices have been discontinued. 1 spia_tx64_err_1 fpga core packet error indication. a '1' indicates an error has occurred for the current packet being transmitted. the err signal must be asserted coincident with the eop signal. when an eop is detected by the dpram write pointer logic, the address pointer will be automatically incremented to the next location within the fifo partition range. spia_tx64_we_1 fpga core write enable. a logic '1' causes data on the spia_tx64_data_1[63:0] bus to be captured for a write to the dpram. spia_tx64_port_1[7:0] fpga core spi4 port indicator, used to associate the current transmit data with a par- ticular port number. spia_tx64_wd_cnt_rst_ 1 fpga core line write termination indicator. this signal causes the fifo write address pointer within the embedded core to increment to the next address location for the addressed partition. this signal can be used for custom applications as well as for diagnostic test functions. spia_tx64_link_dis_1 fpga core link disable control signal. when asserted to a logic '1', the ama will cease polling from a dpram. all ports associated with a disabled dpram will remain unserviced until the control signal is deasserted. the ama will send idle data across the spi4 link. if the application continues to write data to that port fifo, it will eventually ?l and provide proper fifo ?l status to the application. spia_tx64_clk_1 fpga core transmit write clock reference. the clocks across the different transmit interfaces are independent from each other, and are not required to be syn- chronous to each other. spia_tx64_fifo_full_1 core fpga fifo full status. the status is given in response to the assertion of any valid address on the spia_tx64_addr_1[2:0] bus. this signal will be asserted to a logic '1' when the current fifo partition has crossed the con- ?ured ?l level within the partition. status /os spia_tx64_port_id[7:0] core fpga port number of the currently serviced spi4 data port. the value can either be the actual spi4 value or a programmed user value. further details are provided in the tx calendar control logic description. spia_tx64_stat[1:0] core fpga status of the spi4 port currently being serviced. these signals can be used in conjunction with the fifo partition fifo to police transmit traf? congestion for a particular spi4 port. spia_tx64_burst_val[3:0] core fpga indicates the number of spi4 cycles the currently active port will be ser- viced. each cycle indicates an attempt to read 128 bits of data from the respective fifo partition. spia_trefclk_x8 fpga core transmit reference clock. this clock signal is 1/4th the spi4 clock. this sig- nal can be used to synchronize fpga application logic to the fpsc logic. misc. i/os spi_satm_a fpga core ? - incoming atsclk is assumed to be edge-aligned with the data and centered to the data eye within the chip. ? - incoming atsclk is assumed to be skewed with respect to the data off-chip. table 4. spia core transmit fpga interface in 128-bit mode dpram fpga interface i/os direction from/to description 0 spia_tx128_addr[2:0] fpga core virtual fifo write address. each dpram can be divided up to a maximum of eight partitions. when operating in 128-bit mode, each partition will be 4x the depth of the corresponding partition in 32-bit mode. more than one port can be con?ured to share a virtual fifo partition. spia_tx128_data[127:0] fpga core user write data. a single write will complete an entire 128-bit line. note: for spib replace a with b table 3. spia core transmit fpga interface in 64-bit mode (continued) dpram fpga interface i/os direction from/to description note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 38 1036-pin ftsbga devices have been discontinued. 0 spia_tx128_be[15:0] fpga core byte enables indicating which bytes within the 128-bit word are valid. bit[15]-byte enable for spia_tx128_data[127:120] bit[14]-byte enable for spia_tx128_data[119:112] bit[13]-byte enable for spia_tx128_data[111:104] bit[12]-byte enable for spia_tx128_data[103:96] bit[11]-byte enable for spia_tx128_data[95:88] bit[10]-byte enable for spia_tx128_data[87:80] bit[9]-byte enable for spia_tx128_data[79:72] bit[8]-byte enable for spia_tx128_data[71:64] bit[7]-byte enable for spia_tx128_data[63:56] bit[6]-byte enable for spia_tx128_data[55:48] bit[5]-byte enable for spia_tx128_data[47:40] bit[4]-byte enable for spia_tx128_data[39:32] bit[3]-byte enable for spia_tx128_data[31:24] bit[2]-byte enable for spia_tx128_data[23:16] bit[1]-byte enable for spia_tx128_data[15:8] bit[0]-byte enable for spia_tx128_data[7:0] if no be bits are asserted for a particular location within the dpram, data will be dropped and no write to the dpram will occur. according to the spi-4.2 speci?ation, the be bits must be asserted for all but the last transfer, where an end of packet or error may occur. the valid combinations of be are as follows: be[15:0] = 1111111111111111--indicates all sixteen bytes contain valid user data. if an eop is present, it resides within the sixteenth byte. be[15:0] = 1111111111111110--indicates ?teen bytes are valid. eop occurs in ?teenth byte. be[15:0] = 1111111111111100--indicates fourteen bytes are valid. eop occurs in fourteenth byte. be[15:0] = 1111111111111000-indicates thirteen byte is valid. eop occurs in thirteenth byte. be[15:0] = 1111111111110000--indicates twelve bytes are valid. eop occurs in twelfth byte. be[15:0] = 1111111111100000-indicates eleven bytes are valid. eop occurs in eleventh byte. be[15:0] = 1111111111000000--indicates ten bytes are valid. eop occurs in tenth byte. be[15:0] = 1111111110000000--indicates nine bytes are valid. eop occurs in ninth byte. be[15:0] = 1111111100000000--indicates eight bytes are valid. eop occurs in eight byte. be[15:0] = 1111111000000000--indicates seven bytes are valid. eop occurs in seventh byte. be[15:0] = 1111110000000000--indicates six bytes are valid. eop occurs in sixth byte. be[15:0] = 1111100000000000-indicates ?e byte is valid. eop occurs in ?th byte. be[15:0] = 1111000000000000--indicates four bytes are valid. eop occurs in fourth byte. be[15:0] = 1110000000000000-indicates three bytes are valid. eop occurs in third byte. be[15:0] = 1100000000000000--indicates two bytes are valid. eop occurs in second byte. be[15:0] = 1000000000000000--indicates one byte is valid. eop occurs in ?st byte. spia_tx128_sop fpga core start of packet indicator. a '1' indicates the start of packet for a particular port. when operating in 128-bit mode, the sop indicator must be asserted coincident with the ?st line write to the fifo partition in order to align the start of packet data with the sop sideband signal. table 4. spia core transmit fpga interface in 128-bit mode (continued) dpram fpga interface i/os direction from/to description note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 39 1036-pin ftsbga devices have been discontinued. 0 spia_tx128_eop fpga core end of packet indicator. a '1' indicates the end of packet for a particular port. when an eop is detected by the dpram write pointer logic, the address pointer will be automatically incremented to the next location within the fifo partition range. spia_tx128_err fpga core packet error indication. a '1' indicates an error has occurred for the current packet being transmitted. the err signal must be asserted coincident with the eop signal. spia_tx128_we fpga core write enable. a logic '1' causes data on the spia_tx128_data_0[127:0] bus to be captured for a write to the dpram. spia_tx128_port[7:0] fpga core spi4 port indicator, used to associate the current transmit data with a par- ticular port number. spia_tx128_wd_cnt_rst fpga core line write termination indicator. this signal causes the fifo write address pointer within the embedded core to increment to the next address location for the addressed partition. this signal can be used for custom applications as well as for diagnostic test functions. spia_tx128_link_dis_0 fpga core link disable control signal. when asserted to a logic '1', the ama will cease polling from a dpram. all ports associated with a disabled dpram will remain unserviced until the control signal is deasserted. the ama will send idle data across the spi4 link. if the application continues to write data to that port fifo, it will eventually ?l and provide proper fifo ?l status to the application. spia_tx128_clk fpga core transmit write reference clock. there is a single clock per spi4 interface when operating in 128-bit mode. spia_tx128_fifo_full core fpga fifo full status. the status is given in response to the assertion of any valid address on the spia_tx128_addr[2:0] bus. this signal will be asserted to a logic '1' when the current fifo partition has crossed the con- ?ured ?l level within the partition. status i/os spia_tx128_port_id[7:0] core fpga port number of the currently serviced spi4 data port. the value can either be the actual spi4 value or a programmed user value. further details are provided in the tx calendar control logic description. spia_tx128_stat[1:0] core fpga status of the spi4 port currently being serviced. these signals can be used in conjunction with the spia_tx32_port_id signal to police trans- mit traf? congestion for a particular spi4 port. spia_tx128_burst_val[3: 0] core fpga indicates the number of spi4 cycles for which the currently active port will be serviced. each cycle indicates an attempt to read 128 bits of data from the respective fifo partition. atrefclk_f core fpga transmit reference clock. this clock signal is 1/4th the spi4 clock. this sig- nal can be used to synchronize fpga application logic to the fpsc logic. spia_trefclk_x8 fpga core quarter-rate transmit reference clock. this fpga-sourced clock reference must be 2x the desired transmit spi4 line clock rate. when not operating the transmit spi4 core in quarter-rate mode, this signal should be tied off. ex: for a 100 mhz transmit spi4 line clock, spia_trefclk_x8 from the fpga must be 200 mhz. misc. i/os spi_satm_a fpga core ? - incoming atsclk is assumed to be edge-aligned with the data and centered to the data eye within the chip. ? - incoming atsclk is assumed to be skewed with respect to the data off-chip. table 4. spia core transmit fpga interface in 128-bit mode (continued) dpram fpga interface i/os direction from/to description note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 40 1036-pin ftsbga devices have been discontinued. i/o modes - spi4 fpga/embedded core data protocol in order to successfully transmit data across the transmit spi4 link, there is a certain protocol that the data and control signals must obey. this section outlines the fpga/embedded core interface protocol to follow for each of the operating modes of the transmit spi4 embedded core. as mentioned, there are three basic modes of operation when transmitting data into the embedded core from the fpga. for all modes of operation, data is transferred syn- chronous to the rising edge of the respective spi_tx_clk signals. the following ?ures detail the write protocol de?ed for transmitting spi4 transmit data. figure 11 below shows basic interface signals for 32-bit mode of oper- ation. figure 11. basic 32-bit data write protocol to dpram during clock cycle 1, the fpga asserts the partition address, which indicates which partition within the dpram the data and control signals are to be written to. the write enable signal is also asserted, qualifying all data and control signals. in the ?ure, this is the start of a packet, so the sop signal is also asserted. data is presented to the interface, as well as the byte enable (be) and port id signals. the port id is used to identify the port_id ?ld within the spi4 control word. the be vector is used to qualify which bytes on the spi4 transmit link are valid data. during clock cycle 4, the internal dpram write is automatically incremented, and the user is expected to continue write accesses to the fifo partition. during clock cycle 8, the be bits are set to 0xc, indicating only two of the four bytes contain valid packet data. during clock cycle 8, the fpga indicates an end of packet condition for the current selected port. asserting the eop signal causes the internal logic to terminate writes to the current port, as well as automatically incrementing to the next address for the fifo partition. the port id signal should be asserted during an entire write sequence. at a minimum, it must be asserted at least during the last write to the current dpram address line (i.e. for every 128 data bits that are in a dpram location). in the ?ure above, the port id must be asserted during clock cycles 4 and 8. internal to the embedded core is logic that advances the write pointer for each dpram partition. although not visi- ble to the fpga, the internal dpram pointer logic advances to the next valid address within partition range after every 4 writes when in 32-bit aggregation mode. note: spib is identical to spia spia_tx32_clk spia_tx32_wd_cnt_rst spia_tx32_addr[2:0] spia_tx32_we spia_tx32_data[31:0] spia_tx32_sop spia_tx32_eop spia_tx32_port[7:0] spia_tx32_be[3:0] 1234567 8910 partition addr 'k' 0xf 0xf 0xf 0xf 0xf 0xc 0xf 0xf port 3 port 3 lattice semiconductor orca orspi4 data sheet 41 1036-pin ftsbga devices have been discontinued. figure 12 shows 32-bit write timing using fast back-to-back transfers. figure 12. 32-bit write protocol using fast back-to-back transfers during clock cycle 1, the fpga asserts the partition address, which indicates which partition within the dpram the data and control signals are to be written to. the write enable signal is also asserted, qualifying all data and control signals. in the ?ure, this is the start of a packet, so the sop signal is also asserted. data is presented to the interface, as well as the byte enable (be) and port id signals. the port id is used to identify the port_id ?ld within the spi4 control word. the be vector is used to qualify which bytes on the spi4 transmit link are valid data. during clock cycle 4, the fpga has completed writing an entire 128-bit line to the addressed dpram partition and begins an access to another partition commencing with clock cycle 5. since there was no eop presented during clock cycle 4, port 3 must be revisited later with the remaining packet data and required eop. the internal dpram write is automatically incremented at the end of clock cycle 4 as well. during clock cycle 5, port 7 is addressed as the destination partition for the next 128-bit line burst sequence. during clock cycle 8, the be bits are set to 0x8, indicating only one of the four bytes contain valid packet data. the eop signal is also asserted during clock cycle 8 indicating the end of packet for the currently active port 7. asserting the eop signal causes the internal logic to terminate writes to the current port, as well as automatically incrementing to the next address for the fifo partition. during clock cycle 10, the fpga returns to port 3, completing the packet with two 32-bit bursts, and asserting the eop during the latter write cycle. all be bits set to a logic ? during the second write indicates all four bytes of the write are valid. as shown, data may be written to different ports, in a fast back-to-back fashion, without any reduction in data throughput. some points to note are: according the spi4 speci?ation, the smallest packet that may be transmitted across the transmit spi4 link con- sists of a single 16-byte transfer. this means a single occurrence of sop and eop may occur within any dpram location. according to the spi4 speci?ation, only a single port's data may occur within a 16-byte cycle. as a consequence, data from a single port is permitted to be written to any single 128-bit location within the dpram partitions. spi_tx32_clk spi_tx32_wd_cnt_rst 12 34 56 7 spi_tx32_addr[2:0] spi_tx32_we spi_tx32_data[31:0] spi_tx32_sop spi_tx32_eop spi_tx32_port[7:0] spi_tx32_be[3:0] 8910 internal dpram write ptr. 11 addr 'm' addr 'n' addr 'n+1' 'm+1' note: spib is identical to spia port 3 port 7 port 3 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x8 0xf 0xf partition addr 'k' addr 'k+1' addr 'k' lattice semiconductor orca orspi4 data sheet 42 1036-pin ftsbga devices have been discontinued. the sop must always be written into the ?st byte location of the 16-byte dpram word. (shown in figure 7 for the 32-bit interface mode.) with the lattice spi4 interface, the eop may occur during any of the four 4-byte mode writes to ?l the 16-byte dpram, and will be associated with the correct 128-bit line within the partition memory. the next two ?ures show the 64-bit write protocol from the fpga to the tx dprams. it is functionally identical to the 32-bit mode, except two writes are required to ?l an address line within a fifo partition instead of four. figure 13 shows the basic interface signals for 64-bit mode of operation. figure 13. basic 64-bit data write protocol to dpram during clock cycle 1, the fpga asserts the partition address, which indicates which partition within the dpram the data and control signals are to be written to. the write enable signal is also asserted, qualifying all data and control signals. from the ?ure, this is the start of a packet, so the sop signal is also asserted. data is presented to the interface, as well as the byte enable (be) and port id signals. the be vector is used to qualify which bytes on the spi4 transmit link are valid data. when operating in 64-bit mode, there are 8 be bits. during clock cycle 6 the be bits are set to 0xfe, indicating 7 of the eight bytes contain valid packet data. as with 32-bit mode, the port id signal should be asserted during an entire write sequence, although as a minimum it must be asserted at least during the second write to the current dpram address line. in the ?ure above, the port id must be asserted during clock cycles 2, 4, and 6. during clock cycle 6, the fpga indicates an end of packet condition for the current selected port. asserting the eop signal causes the internal logic to terminate writes to the current port. also, the internal dpram pointer logic is advanced after every second write to the dpram when in 64-bit aggregation mode. as with the 32-bit aggregation mode, the ?nternal dpram write ptr advances to the next valid address within par- tition range, but after every 2 writes when in 64-bit aggregation mode. this is because two 64-bit writes ?l an entire 128-bit dpram line entry. the same interface logic in the fpga can also be used as described in 32-bit mode, but the counter implemented in fpga logic is simply a one-bit toggle ff. spia_tx64_clk spia_tx64_wd_cnt_rst 123456 7 spia_tx64_addr[2:0] spia_tx64_we spia_tx64_data[63:0] spia_tx64_sop spia_tx64_eop spia_tx64_port[7:0] spia_tx64_be[7:0] note spib is identical to spia port 3 port 3 0xff 0xff 0xff 0xfe 0xff 0xff partition addr 'k' port 3 lattice semiconductor orca orspi4 data sheet 43 1036-pin ftsbga devices have been discontinued. figure 14. 64-bit write protocol using fast back-to-back transfers as with figure 13, the fpga initiates the start of a packet by asserting the fifo partition address, we, data and other pertinent control signals in figure 14. during clock cycle 2, an entire 128-bit line has been written and the internal logic increments it s write pointer to the next location within the fifo partition. during clock cycle 3, the fpga begins writing to a different dpram fifo using a back-to-back transfer. a new partition address and port id are presented to the dpram. since this is the start of the packet, the sop is asserted. during clock cycle 5, the internal write pointer is advanced to the next address within the fifo partition range. on clock cycle 6, the fpga terminates the packet by asserting the eop signal. the internal dpram write pointer advances during clock cycle 6 to the next location and then waits for the fpga to attempt another write access to a partition within the dpram. beginning with clock cycle 7, the fpga resumes writing to the original port. the fpga presents the correct parti- tion address and asserts the required control signals. the internal write pointer decodes the partition address and sets the internal write pointer to address 'n+1'. as with 32-bit mode, in 64-bit aggregation mode, data may be writ- ten to different ports in a fast back-to-back fashion without any reduction in data throughput. during clock cycle 8, the fpga terminates writing to the current packet by asserting the eop input signals and the correct number of be signals. figure 15 below shows the protocol required when operating in 128-bit aggregation mode. a single write from the fpga ?ls an entire line within a fifo partition. spi_tx64_clk spi_tx64_wd_cnt_rst 123456 7 spi_tx64_addr[2:0] spi_tx64_we spi_tx64_data[63:0] spi_tx64_sop spi_tx64_eop spi_tx64_port[7:0] spi_tx64_be[7:0] internal dpram write ptr. 8 addr 'n' addr 'm' 'm+1' 'n+1' note: spib is identical to spia part. addr 'k' part. addr 'k' partition addr 'k+4' 0xff 0xff 0xff 0xff 0xff 0xfc 0xff 0xc0 port 7 port 3 port 3 lattice semiconductor orca orspi4 data sheet 44 1036-pin ftsbga devices have been discontinued. figure 15. 128-bit write protocol spi4 transmit interface - detailed description the fpga transmit interface provides a simple fifo-like interface, simplifying write accesses. asserting the cor- rect 3-bit address with the associated write enable signal causes transmit data and sideband control signals to be registered for writes to a fifo partition within the dprams. when addressing a particular fifo partition within the dpram, the associated fifo ?l level of the addressed partition is immediately re?cted back to the fpga, enabling the user to monitor the current ?l level of a particular partition. based upon the con?ured ?l level, a logic '1' on the fifo_full signal will indicate either a 3/4-full condition or a completely full condition for the indexed par- tition. transmit dprams there are four dprams referred to as banks 0, 1, 2 and 3. each bank has a 32-bit data interface to the fpga. each dpram has its own individual write enable and write clock allowing it to be written by the fpga application independently. each dpram bank is con?ured by software to operate in either 32-bit, 64-bit or 128-bit aggregation mode. every dpram bank is also con?ured to contain 1, 2, 4 or 8 virtual fifos. the user determines the number of fifos depending on the number of ports and buffer requirements for the ports as required by a given application. the pro- gramming of a dpram bank in 32-bit, 64-bit or 128-bit mode and programming of the number of virtual fifos within a dpram bank is done through software as shown in table 8. note that in 64-bit mode, dprams 0 and 1 must be con?ured identically. the combined dpram pair is referred to as dpram ?? similarly dpram pairs 2 and 3 must be con?ured identically. this combined dpram pair is referred to as dpram ?? in 128-bit mode, all dprams must be con?ured identically. the combined dpram banks are collectively referred to as dpram ?? the aggregation modes can be used in ?e possible combinations as shown in table 6. the size of the embedded data and control fifos for each mode is shown in table 7. the user accesses a virtual fifo using the 3-bit fifo read address (refer to table 2, table 3, and table 4) from the fpga. table 5 shows the indexed partition based upon the con?ured dpram partitioning and aggregation mode. spia_tx128_clk spia_tx128_wd_cnt_rst 123 4 5 6 spia_tx128_addr[2:0] spia_tx128_we spia_tx128_data[127:0] spia_tx128_sop spia_tx128_eop spia_tx128_port[15:0] spia_tx128_be[7:0] part. addr 'k' 0xffff port 3 port 7 port 2 addr 'j' note: spib is identical to spia 0xffff 0xfff8 0xffff 0xffff partition addr 'j+4' lattice semiconductor orca orspi4 data sheet 45 1036-pin ftsbga devices have been discontinued. table 5. fifo address based on programmed virtual fifos table 6. possible combinations of aggregation modes within the embedded core, data is quad-word aligned, and written to the dprams only on 128-bit boundaries. when operating in 32-bit or 64-bit mode, with the exception of eop terminated write accesses, either 4 or 2 write accesses, respectively, must be performed before the internal fifo address pointer can be incremented to the next location. it is required for the fpga to perform all data writes on 128-bit boundaries. thus, the application will write entire ?ines to the dpram causing the internal address pointer to increment to the next location in memory. if the fpga attempts to write to a fifo partition within the dpram and none of the 16 be bits are set, the data will not be written into the fifo and the internal write pointers will not be advanced. this is done to prevent erroneous data from being sent across the spi4 link, as well as optimize fifo memory usage. link disable under certain circumstances, the application may require the spi4 interface to disable a particular dpram from being serviced. to accommodate this, the user can assert the proper 'link disable (link_dis) signal indicating to the dpram logic to stop service to a particular dpram. as long as the assertion of the link_dis for a particular partition is asserted, all partitions within the associated dpram will not be serviced. if the application attempts to perform further writes to any of the disabled fifo partitions, data will be accepted up to the point the fifo becomes full. after the fifo ?ls, data will no longer be accepted. data written to the disabled dpram will remain latent within the memory. upon removal of the link disable signal, ports from the enabled dpram will be serviced according to the con?ured calendar sequence. the following is an example of the effect of asserting a link disable. for this example, assume the orspi4 is con- ?ured as follows: spi[a,b]_tx_addr[2:0] description xxx bits are ignored when the dpram is con?ured to support a single partition. (device select bits can be set to any value in single partition mode). 000 selects partition 0 when the dpram is con?ured to support 2, 4 or 8 partitions. 001 selects partition 1 when the dpram is con?ured to support 2, 4 or 8 partitions. 010 selects partition 2 when the dpram is con?ured to support 4 or 8 partitions. 011 selects partition 3 when the dpram is con?ured to support 4 or 8 partitions. 100 selects partition 4 when the dpram is con?ured to support 8 partitions. 101 selects partition 5 when the dpram is con?ured to support 8 partitions. 110 selects partition 6 when the dpram is con?ured to support 8 partitions. 111 selects partition 7 when the dpram is con?ured to support 8 partitions. mode valid banks 0 to 3 in 32-bit aggregation mode yes banks 0, 1 in 64-bit aggregation mode, banks 2,3 in 64-bit mode ye s banks 0,1 in 64-bit mode, banks 2 & 3 in 32-bit mode ye s banks 0,1 in 32-bit mode, banks 2 & 3 in 64-bit mode ye s all banks in 128-bit yes bank 0 in 32-bit mode, bank 1 in 64-bit mode or vice-versa no bank 2 in 32-bit mode, bank 3 in 64-bit mode or vice-versa no lattice semiconductor orca orspi4 data sheet 46 1036-pin ftsbga devices have been discontinued. both spi-4 a and b are enabled 32-bit aggregation for all banks furthermore, assume the con?uration of the spi-4 is as follows: transmit calendar has 4 ports: 0,1, 2, and 3 transmit dprams con?ured to 1 partition each transmit pdm assigns burst value of 4 to each port transmit pdm maps port 0 to bank 0, port 1 to bank 1, port 2 to bank 2, and port3 to bank 3 figure 16 shows how the port polling changes when the link disable for bank 1 is asserted (input signal spib_tx32_link_dis_1 in this con?uration). before spib_tx32_link_dis_1 is asserted, the normal port poll- ing sequence ?0, 1, 2, 3, 0, 1, 2, 3, 0, ? ?is seen on the spib_tx32_port_id outputs. each port poll lasts for the programmed burst value (4 in this example) number of cycles. after the spib_tx32_link_dis_1 high transi- tion, the sequence of port ids changes to 0, 2, 3, 0, 2, 3, 0, ?. note that the duration of port 0 is now 6 cycles with port 1 disabled. the 2 extra cycles are needed by the port poll sequencer to skip over port 1 and continue to port 2. the port poll sequencer does not read data from bank 0 dur- ing these 2 extra cycles, so they may be considered idle cycles. before spib_tx32_link_dis_1 was asserted, the port polling period was 4 ports x 4 cycles/port = 16 cycles. after spib_tx32_link_dis_1 is asserted, the port polling period becomes 3 ports x 4 cycles/port + 2 extra cycles = 14 cycles. figure 16. port 1 disable figure 17 shows how the port polling changes when a second bank is disabled. here the signal spib_tx32_link_dis_2 is asserted to disable port 2. the port polling period with two ports disabled becomes 2 ports x 4 cycles/port + 4 extra cycles = 12 cycles. 01230123 0 23 0 2 spib_tx32_port_id[7:0] spib_tx32_link_dis_3 spib_tx32_link_dis_2 spib_tx32_link_dis_1 spib_tx32_link_dis_0 spib_tx32_clk_0 lattice semiconductor orca orspi4 data sheet 47 1036-pin ftsbga devices have been discontinued. figure 17. port 1 and 2 disable tx dpram the tx dprams consist of four 256 x 160 memories, that can each be partitioned into a maximum of 8 equally sized virtual partitions, providing a maximum of 32 virtual fifo partitions. by providing a simple fifo-like interface to the fpga, the fpga can access fifo partitions by asserting a 3-bit address ?ld. internal logic maintains both write and read pointers and provides a programmable fifo_full ?g to the fpga logic in order to prevent over- ?w conditions. data may be written into the dprams using either multiple 32-, or 64-bit interfaces, or alternatively using a single 128-bit interface. the sideband control bus is present for each individual interface. the dpram partition depths are a function of the interface width used, as well as the number of con?ured partitions. table 7 shows the depth of virtual partitions for data and sideband control information based upon the write interface width and the number of partitions. table 7. memory size for each aggregation mode and partitioning write interface mode # of con?ured virtual fifo partitions data fifo depth (in bytes) control fifo depth (in bytes) 32-bit 1 2k 512 2 1k 256 4 512 128 8 256 64 64-bit 14k 1k 2 2k 512 4 1k 256 8 512 128 128-bit 18k 2k 24k 1k 4 2k 512 8 1k 256 023023 0 30 3 spib_tx32_port_id[7:0] spib_tx32_link_dis_3 spib_tx32_link_dis_2 spib_tx32_link_dis_1 spib_tx32_link_dis_0 spib_tx32_clk_0 0 lattice semiconductor orca orspi4 data sheet 48 1036-pin ftsbga devices have been discontinued. partitioning of the dual port rams is done through customer programmable registers. table 8 below shows regis- ter settings for aggregation mode and partition size. table 8. register settings for aggregation mode and partition size. dpram aggregation mode address 30903 (spia), 30a30 (spib) virtual fifo partition size address 30927 (spia), 30a27 (spib) con?uration dpram 0 (register bits 0:1) = 00 register bits 0:1 = 00 32-bit data width, partition size 1 01 32-bit data width, partition size 2 10 32-bit data width, partition size 4 11 32-bit data width, partition size 8 01 00 64-bit data width, partition size 1 01 64-bit data width, partition size 2 10 64-bit data width, partition size 4 11 64-bit data width, partition size 8 10 00 128-bit data width, partition size 1 01 128-bit data width, partition size 2 10 128-bit data width, partition size 4 11 128-bit data width, partition size 8 dpram 1 (register bits 2:3) = 00 register bits 2:3 = 00 32-bit data width, partition size 1 01 32-bit data width, partition size 2 10 32-bit data width, partition size 4 11 32-bit data width, partition size 8 01 00 64-bit data width, partition size 1 01 64-bit data width, partition size 2 10 64-bit data width, partition size 4 11 64-bit data width, partition size 8 10 00 128-bit data width, partition size 1 01 128-bit data width, partition size 2 10 128-bit data width, partition size 4 11 128-bit data width, partition size 8 dpram 2 (register bits 4:5) = 00 register bits 4:5 = 00 32-bit data width, partition size 1 01 32-bit data width, partition size 2 10 32-bit data width, partition size 4 11 32-bit data width, partition size 8 01 00 64-bit data width, partition size 1 01 64-bit data width, partition size 2 10 64-bit data width, partition size 4 11 64-bit data width, partition size 8 10 00 128-bit data width, partition size 1 01 128-bit data width, partition size 2 10 128-bit data width, partition size 4 11 128-bit data width, partition size 8 lattice semiconductor orca orspi4 data sheet 49 1036-pin ftsbga devices have been discontinued. based upon the traf? characteristics of individual ports and number of ports supported, the user can tailor the fifo depth to optimize performance at the fpga/embedded core interface. when operating in 32-bit mode, four write cycles are necessary to complete an entire 128-bit line. 64-bit mode requires 2 write accesses, with 128-bit mode using a single clock per line ?l. when data is read out of the dprams, via the ama logic, it is read using a 128-bit data bus. therefore, for each port serviced, one clock cycle is consumed to read 16 data bytes and 4 control bytes from each addressable loca- tion within a fifo partition. this corresponds to the spi4 requirement that only a single spi4 port's data may exist on the transmit data bus within any burst cycle. a burst cycle is made up of 16 bytes. note, for all modes of aggregation, if an entire 128 bits is written to any fifo partition, with all 16 be bits deas- serted, the quad-word will not be written to the dpram, nor will the internal write pointer be incremented for the selected fifo partition. within the transmit dpram, there are user-programmable ?l level thresholds for each enabled partition. the pro- grammable levels are either 3/4-full or absolutely full. when the ?l level of an addressed partition exceeds the pro- grammed ?l level, a fifo full condition is reported back to the fpga. because the ?l level operates only on 128 bits, the full ?g is only updated after an entire line has been written. the full condition will persist until the fifo has been serviced and the ?l level drops below the programmed ?l threshold. in order to take a dpram temporarily out of service without updating the calendar, the fpga can assert the link disable (spi_tx_link_dis[3:0]) input signal associated with the dpram to be disabled. the fpga is permitted to continue to write data to the disabled port fifo, as it will obey all the functionality described above regarding fifo ?l level and status. when the dpram is to be put back into service, the user simply deasserts the link_dis signal. the associated ports will then be serviced according to the con?ured calendar sequence. address map arbiter (ama) logic block the address map arbiter (ama) logic block is a slave device to the tx calendar control logic. upon receiving a valid ama_id and burst_val vectors, the ama will attempt to read out data from the indexed dpram fifo par- tition along with the associated sideband control signals. in order to take a dpram temporarily out of service without updating the calendar, the fpga can assert the link disable (spi_tx_link_dis[3:0]) input signal associated with the dpram to be disabled. the fpga is permitted to continue to write data to the disabled port fifo, as it will obey all the functionality described above regarding dpram 3 (register bits 6:7) = 00 register bits 6:7 = 00 32-bit data width, partition size 1 01 32-bit data width, partition size 2 10 32-bit data width, partition size 4 11 32-bit data width, partition size 8 01 00 64-bit data width, partition size 1 01 64-bit data width, partition size 2 10 64-bit data width, partition size 4 11 64-bit data width, partition size 8 10 00 128-bit data width, partition size 1 01 128-bit data width, partition size 2 10 128-bit data width, partition size 4 11 128-bit data width, partition size 8 dpram aggregation mode address 30903 (spia), 30a30 (spib) virtual fifo partition size address 30927 (spia), 30a27 (spib) con?uration lattice semiconductor orca orspi4 data sheet 50 1036-pin ftsbga devices have been discontinued. fifo ?l level and status. when the dpram is to be put back into service, the user simply deasserts the link_dis signal. the associated ports will then be serviced according to the con?ured calendar sequence. upon receiving a valid ama_id, the ama logic will service a port by reading data from the fifo partitions for burst_val clock cycles. both data and sideband control signals are read and sent directly to the tdp logic block. in the event a fifo partition becomes depleted before burst_val number of reads is performed, the ama will send idle data to the tdp and will override the associated byte enable (be) control signals, indicating the current data is not user data. this will temporarily reduce the spi4 transmit link data throughput, but will not affect the oper- ation of the transmit link itself. when reading data from fifo partitions, and the fifos are empty, it is possible to gain back some lost data throughput on the spi4 transmit link. enabling the tx_burst_termination control register within the embed- ded core causes the ama to advance to the next port for service within four clock cycles after detecting the fifo is empty. this feature works in conjunction with the tx calendar control logic. upon detecting the currently serviced fifo has run empty, the ama block sends a control signal to the calendar control logic, which then immediately advances to the next location within the calendar and presents a new set of ama_id and burst_val ?lds to the ama block. because there is a four-clock latency between detection of an empty fifo and the assertion of the next port to service, data bandwidth gains can be achieved on ports with larger burst_val values. transmit data protocol (tdp) logic block the transmit data protocol (tdp) block is responsible for receiving and formatting spi4 packet data and all asso- ciated sideband control signals, and formatting the data into the correct spi4 protocol. this block also performs dip-4 calculation, spi4 data word, control word and training control word generation. additionally, this block attempts to perform bandwidth optimization by combining ordered bytes from 2 consecutive 128-bit words from the ama whenever possible. this is done to maximize data throughput on the transmit spi4 link. the tdp provides a small fifo to allow for data buffering in order to concatenate valid bytes with idles. in the event the fifo becomes full, it sends a fifo_full ?g to the transmit calendar control word logic to throttle data transmission. flow control is necessary for small periods of time while training patterns are being sent across the transmit spi4 link. data formatting performed in this block consists of alignment, dip-4 calculation and training pattern generation. aligner: using the sop, eop and port control signals the tdp determines what type of control word is necessary to be transmitted with the corresponding data. using the be bits, the tdp can determine how to concatenate data into sequences of continuous 16 byte bursts whenever possible. dip-4 calculation: after aligning the data and control words, the tdp calculates the odd parity codeword according to the oif spi4 speci?ation. training pattern generation: there are two causes of generating a training sequence for the transmit spi4 link: using the user-programmable tx_data_max_t register, or the tdp receives four or more consecutive '11' patterns from the status block, indicating excess dip-2 errors. using the programmed tx_data_max_t register along with the user-programmable tx_alpha register, the tdp internally counts down the correct number of clock cycles before transmitting training sequences across the trans- mit link. the tx_alpha register is used to indicate the number of training sequences to be sent. when the transmit status receives excessive errors, the status block sends consecutive '11' patterns to the tdp. according to the spi4 speci?ation, the tdp will begin sending training patterns across the spi4 link until the sta- tus error is remedied. lattice semiconductor orca orspi4 data sheet 51 1036-pin ftsbga devices have been discontinued. transmit data output (tdo) logic block the transmit data output (tdo) block contains the high-speed serializer, which uses an x8 clock, synthesized by an internal pll, to generate the high-speed data from the low-speed 128-bit data. data is transmitted off-chip using a 16-bit lvds data bus tdat[15:0], a lvds control bit tctl and a source synchronous clock tdclk. the 16-bit data bus and control are ddr signals relative to the tdclk. the lvds buffers contained within the tdo are fully compliant with spi4 electrical speci?ations. the tdo uses the internal embedded core transmit reference clock (trefclk) to generate an x4 tdclk. the tdclk and trefclk are both derived from the user-provided reference clock. the trefclk is used as the sys- tem clock for the entire transmit spi4 interface logic. the trefclk is also sent to the fpga for the customer to use as a synchronizing signal source if desired. in order to support 10 gbits/s throughput, the minimum frequency of tdclk needs to be 622 mbits/s (311 mhz ddr). for applications that require less than 100 - 200 mbits/s on tdclk, the pll in the tdo block can be bypassed. this allows for operation as low as 100 mhz on the transmit spi4 link. figure 18. transmit calendar and status block transmit calendar (tcc) logic block the transmit calendar block (tcc) is responsible for maintaining the transmit main and shadow calendars, provid- ing port service information to the ama, integrating transmit status update information into the servicing of ports according to the spi4 speci?ation, and providing port service information to the fpga for traf? monitoring. tx calendar control logic tsp tsi atstat atsclk tlstat tlsclk port_id port_stat burst_val to ama ama_id k = 32, 64, or 128 8 spi[a,b]_tx_k_port_id 2 spi[a,b]_tx_k_stat 4 spi[a,b]_tx_k_burst_val to fpga i/f from external i/o note: spia is identical to spib lattice semiconductor orca orspi4 data sheet 52 1036-pin ftsbga devices have been discontinued. figure 19. transmit calendar control logic functional diagram the transmit spi4 interface contains both main and shadow calendars enabling a hitless switch over between an old and new calendar schedule. each calendar is 1023 locations deep, providing a high degree of ?xibility and customizable port service algorithms. the user can con?ure the calendar(s) through software con?uration regis- ters. (see the transmit memory map register set for identi?ation of individual con?uration register addresses). note, in order to effect a hitless switch at the logical port level, the user must ensure that port data associated with any calendar modi?ations have been terminated correctly before the calendar switches. for example, if the shadow calendar eliminates port 3 from the calendar sequence, the user must ensure there is no data associated for port 3 in the fifo partitions when the calendar switches. otherwise, service will be granted for an out-of-ser- vice port, causing higher layer protocol exceptions. the calendar length is also con?urable to indicate the number of valid port entries. programming the calendar_len register indicates how many entries within the transmit calendar are enabled for sequencing. since the calendar is 1023 locations deep, a single port may be serviced more than once per calendar sequence. port service information the tcc sequentially runs through the calendar sequence retrieving the port number that is to be serviced next. the ?ld is an 8-bit vector, supporting the entire 256 possible entries of the spi4 calendar. the retrieved port num- ber is used to index a port descriptor memory (pdm) to retrieve all pertinent information required for maintaining proper port servicing. there are several ?lds within the pdm that are required to be con?ured by the user before the transmit interface can be enabled. a description of the ?lds within the descriptor is given below: port_id - port information sent to the fpga when a port is being serviced. this value is con?urable by the user and can contain either the spi4 number of the port, or can contain an alias the fpga uses to map propri- etary interface channels to the corresponding spi4 port (see the 'm'-bit description below). the fpga logic can also use the port_id for status acquisition, or other link layer ?w control functions. after reset this ?ld defaults to a value of 8'h00. burst_val - port information sent to the fpga (when a port is being serviced) and ama. this user-con?- urable ?ld indicates the maximum number of 16-byte burst accesses the port is permitted to consecutively transmit across the spi4 link, before segmentation must be performed. the fpga can use this ?ld to indicate how much data to source for the port being polled to maintain buffering within the dpram fifo partition. after reset this ?ld defaults to a value of 4'h0. spi[a,b]_tx_stat transmit calendar main/ spi[a,b]_tx_port_id burst_val ama_id 0 255 credit burst_val port seq addr port desc data status update logic port_id port_stat spi[a,b]_tx_burst_val shadow to fpga to ama mb_en m port_id status ama bank_id partition_id port memory descriptor lattice semiconductor orca orspi4 data sheet 53 1036-pin ftsbga devices have been discontinued. ama - this user con?urable ?ld consisting of a dpram bank_id (left-most two bits) and a dpram partition_id, indicates to the ama (ama_id) which physical dpram partition address to poll for port servic- ing. after reset, this ?ld defaults to a value of 5'h00. m - indicates whether the programmed port_id or the seq_port_num contained within the calendar sequence table should be broadcast to the fpga. this is performed on a per port basis, providing a mapping function between proprietary fpga port mapping and the spi4 transmit calendar port number. ex: spi4 port number 138 maps to fpga interface device #7, port #17. when the 'm'- bit is set to a logic one, the pro- grammed port_id (i.e. 138) is broadcast to the fpga for the port being serviced; when set to a logic zero, the port number from the transmit calendar is sent to the fpga for that particular port. after reset, this ?ld should default to a value of 1'b0. credits - indicates the number of bursts the port is permitted to transmit across the spi4 link between status updates, for that particular port. this ?ld is updated with calculated credit values after the port is serviced. whenever the receive status from the tsp block presents a port status value of 2'b11, the credit ?ld for the indexed port is to be cleared to a value of 10'h000. this disables the port. the user may con?ure an initial value for each enable port. after reset, this ?ld is to default to a value of 10'h000. this ?ld should not be altered after the transmit calendar is placed in operation. mb_en - this user-con?urable register indicates whether the associated port supports max_burst parame- ters as de?ed within the spi4 speci?ation. the transmit calendar supports a single tx_max_burst1 and a single tx_max_burst2 value. logic one indicates that the con?ured port supports max_burst. after reset, this ?ld is to default to a value of 1'b0. this is con?urable on a per-port basis. stat - contains transmit fifo status from the tsp block. used in conjunction with the mb_en ?ld to update the credit ?ld for the indexed port. also sent to the fpga for status monitoring. after reset this ?ld is set to a value of 2'h3, indicating the port is disabled. status update logic transmit status is received from the tsp block (described later). both the port number and associated status of the port is sent to the status update logic. this block ensures that the status for each port, as it is received, is updated correctly. the status is received according to the programmed far-end calendar, and will generally be received asynchronously (relative to port servicing) to the local transmit calendar polling. by providing the burst_val, stat, and port_id value to the fpga, application logic can maintain the required data bandwidth it needs to source, in order to keep the respective fifo partition from over/under-?wing. these signals can also be used in conjunction with fpga control logic to oversee the operation of the memory controller for accessing the transmit spi4 port data. transmit status input (tsi) block the transmit status input (tsi) block provides the interface to the spi4 transmit status signals. these signals can be either lvds or lvcmos input buffers. this is selected using the spi4_status_io_sel register setting. the status interface supports quarter-rate mode only, as de?ed within the spi4 speci?ation. the user has the option to use the status input signals either in phase with status input clock, or out of phase with the status input clock, by optionally inverting the input clock signal on-chip. setting spi_satm_a and spi_satm_b registers to a ? will cause them to be in phase, setting to a ? will cause them to be out of phase. the tsi block receives transmit status and provides both the status information and a derived clock to the tsp block. transmit status protocol (tsp) block the transmit status protocol (tsp) block receives status from the tsi block and uses the user-con?ured transmit calendar to associate the current received status with a port. this block performs fifo status decoding, buffering and dip-2 calculations. as de?ed within the spi4 speci?ation, if dip-2 errors occur, it sends an error ?g to the tdp block for processing. the tsp provides port status information to the transmit calendar logic along with the associated port number. the calendar logic then updates the appropriate port stat ?ld. the tsp block also sup- ports hitless bandwidth provisioning as de?ed within appendix g of the spi4 speci?ation. lattice semiconductor orca orspi4 data sheet 54 1036-pin ftsbga devices have been discontinued. transmit calendar operation this section gives a description of how the transmit calendar operates, in order to assist users in understanding how to con?ure the tx spi4 programmable calendar and con?uration registers to ? their application. figure 18 and figure 19 will be used as reference. the transmit calendar logic is synchronous to trefclk for it s internal operations. the transmit calendar logic uses an indirect addressing scheme to acquire port sequence information. this enables the user to con?ure the calendar easily, while minimizing the amount of information that needs to be pro- grammed within the calendar table. indirect addressing also enables users to con?ure the entire port descriptor memory at initialization time, without having to actually enable all the entries. the user has access to modify port information within the pdm at any time, whereas the calendar(s) can only be updated while it is not in service. the transmit calendar sequentially runs through all the user-enabled port entries within the 1k memory. the cal- endar rolls over to the ?st entry whenever the user-con?ured maximum calendar length is reached. the time between polling the same port is a function of the several factors, including user-con?ured burst_val per port, and whether the tx_burst_termination is enabled (set to logic ??. the user must con?ure the tx_cal_len_main to indicate the number of valid entries to sequence through in the main calendar. not all applications require 1023 locations to be polled. if the shadow calendar is to be used, the user must con?ure the tx_cal_len_shd to indicate the number of valid entries to sequence in the shadow calendar. the shadow calendar is independent of the main calendar, and may have a different number of entries. the user must either enable tx_burst_termination or leave it disabled. by default it is disabled. when a port is indexed within the calendar, the indexed vector serves as the address to the port descriptor mem- ory, to fetch all the necessary information to service the selected port. the port descriptor memory (pdm) provides 256 entries; one for each possible spi4 port. the pdm contains all the port servicing control information. when a port is indexed via the calendar, the calendar pointer is incremented to the next location, serving as a pseudo prefetch in case tx_burst_termination is enabled. every time a port is indexed in the pdm, an internal counter loads burst_val and begins decrementing. upon nulling out, the next calendar entry is used to index the pdm to fetch the next port to be serviced. again, the calendar advances to the next enabled location. as de?ed within the spi4 speci?ation, burst_val indicates the number of 16-byte cycles a port may be serviced before segmentation must occur. using burst_val, the transmit calendar can maintain constant port servicing from the dual port memories. the user must con?ure a burst_val value for each enabled spi4 port. the pdm contains 256 locations, i.e. one for each possible spi4 port. the transmit calendar broadcasts the ama_id and burst_val vectors, fetched from the pdm, to the ama block. the ama will use the id value to address the physical entry of the port that is to be serviced. note the ama_id value is the physical address of the dpram and is made up of two user-con?urable ?lds, the partition_id and bank_id. the dprams consist of 4 banks, and each may be partitioned into a maximum of 8 virtual fifos each. the user must con?ure both the partition_id[2:0] and bank_id[1:0] ?lds for each enabled port within the pdm. the partition_id vector is identical to the spia_tx32_addr_0[2:0]. the user con?ures the same partition address for a particular port that is used as the address on transmit dpram write interface. the bank_id vector is simply derived from the physical interface used at the fpga/embedded core interface, as shown below. 32-bit mode [00,01,10,11], providing up to 4 interfaces 64-bit mode [00, 01], providing up to 2 interfaces 128-bit mode [00], providing a single interface for all combinations of aggregation, the values given above apply. more than one port can be mapped to the same partition. simply program the same partition_id and bank_id values in all the pdm port entries that share the same partition. lattice semiconductor orca orspi4 data sheet 55 1036-pin ftsbga devices have been discontinued. the transmit calendar also broadcasts the burst_val, current status and either the transmit calendar entry vector or a user-con?urable port value to the fpga. selection between the calendar vector and the con?ured value is decided with the 'm'-bit. when logic '0', the calendar port vector is broadcast to the fpga. otherwise, the user-con?urable port_id ?ld is sent. the optional port_id is provided in order to assist the fpga in mapping it's proprietary channel/port numbers to the spi4 calendar port value. by con?uring the port_id value and set- ting the 'm'-bit for particular ports, the fpga will receive the programmed value instead of the spi4 port number. this feature is very useful when the user is sharing a particular fifo partition within the dpram between multiple ports. providing these ?lds to the fpga enables users to updated statistics of port servicing for external data schedulers and the external memory controller. if the user desires to have proprietary channel/port values broadcast to the fpga, the 'm'-bit must be set to a logical ?? and the associated port_id ?ld must be con?ured to the desired value. this is done on a per port basis, so some ports may be mapped, while others use the transmit calendar index vector. if the user maps more than one port to the same fifo partition, the user is free to choose which port id ?ld is sent to the fpga. as ports are serviced, their credit ?lds are updated according to the requirements as de?ed within the spi4 speci?ation. although not commonly used, the transmit spi4 calendar logic allows the user to con?ure the credit ?ld with an initial value at con?uration time. this is useful for some applications as well as providing diag- nostic and test capabilities of the calendar update logic. the transmit calendar also supports single maxburst1 & maxburst2 values, as de?ed within spi4. the mb_en ?ld is enabled on a per-port basis and indicates whether the associated port differentiates between the de?ed hungry and starving states. when the mb_en bit is set to a logical ?? that particular port uses both the maxburst1 and maxburst2 ?lds: otherwise only the maxburst1 ?ld is associated with the port s credit ?ld update algorithm. in order to use the maxburst1 and maxburst2 ?lds, the user must program both ?lds to the required values. by default the value for these registers is ?? the user must either con?ure the mb_en ?ld for each port to a logical ? if the port have it s credit ?ld updated using the maxburst2 ?ld. by default the maxburst2 values are not used in the credit update calculation. the user can optionally con?ure the credit ?ld to a particular value if desired, although it is not necessary for most applications. during normal operation, transmit status is received on a per port basis. the status ?ld for each port is updated independent of where the transmit calendar polling exists. internal logic prevents updates to be performed on a port while it is in use. although uncommon, the spi4 transmit calendar allows the user to con?ure the stat ?ld to some value, but only during initialization. this is intended to be used for diagnostics or for some other proprietary applications. under normal operation, the user can ignore this function. the user can program the stat[1:0] ?ld for as many ports as desired within the pdm. when a hungry status indication is received, transfers up to maxburst2 16-byte blocks or the remainder of what was previously granted (whichever is greater) may be sent to the corresponding port prior to the next status update. a starving status indication indicates that buffer under?w is imminent in the corresponding phy port. when starving is received, transfers for up to maxburst1 16-byte blocks may be sent to the corresponding port prior to the next status update. internal to orspi4, the ?6-byte blocks term is also called burst_val. even though the maxburst1 and maxburst2 are global parameters for all the ports, each port has its own burst_val parameter attached to it that the user must program in the transmit port descriptor memory (txpdm). every time the tx sta- tus is updated for a port, maxburst1 or maxburst2 values are loaded into the credits ?ld for that particular port. from that point on until a new tx status update takes place, data is sent according to the following ?w-chart. lattice semiconductor orca orspi4 data sheet 56 1036-pin ftsbga devices have been discontinued. figure 20. port credit field update flow chart table 9 below shows the spi4 status update de?itions. table 9. spi4 status field de?ition when transmitting across the spi4 link, typically for clock speeds in excess of 350 mhz, dynamic alignment is required to maintain a coherent data link. in conjunction with dynamic alignment, spi4 outlines a training protocol that is periodically used to maintain receive data integrity. the spi4 transmit core supports data training through the use of a 32-bit variable named tx_data_max_t. this 32-bit variable indicates the number of clock cycles that will occur between training sequences. spi4 also de?es an tx_alpha variable indicating the number of times the training pattern is to be repeated during a training session. the tdp supports both these variables allowing the user to tailor both of these parameters to ? their particular environment and dynamic traf? requirements. the user must con?ure the 32-bit tx_data_max_t variable to indicate the number of clock cycles that should lapse between training sequence. a value of 0x00000000 disables training. by default training is disabled. msb lsb description: 1 1 reserved for framing or indicate a disabled status link. 10 satisfied indicates the corresponding port's fifo is almost full. when satisfied is received, only transfers using the remaining previously granted 16-byte blocks (if any) may be sent to corresponding port until the next status update. no additional transfers to that port are permitted while satisfied is indicated. 01 hungry when hungry is received, transfers for up to maxburst2 16-byte blocks or the remainder of what was previously granted (whichever is greater), may be sent to the corresponding port until the next status update. 00 starving indicates that buffer under?w is imminent in the corresponding phy port. when starving is received, transfers for up to maxburst1 16-byte blocks may be sent to the corresponding port until the next status update. start tx status update status mb_en credits = maxburst1 credits = maxburst2 data sent = burst_val * 128 bits data sent = | (credits - burst_val) | * 128 bits credits = | (credits - burst_val) | no yes no yes hungry satisfied starving lattice semiconductor orca orspi4 data sheet 57 1036-pin ftsbga devices have been discontinued. if training is to be used, the user must also con?ure the 16-bit tx_alpha variable to indicate the number of times the training pattern is to be repeated. by default the value is 0x0000 which disables the training pattern. if the number of bytes within the training sequences do not ?l entire spi4 burst cycle, the unused byte ?lds will be padded with idle data in order to keep the training sequences aligned on 16 byte boundaries. calendar programming on a spi4 link, fifo status information is received periodically over the status link (tstat bus on the spi4 inter- face) from the device that sources data. calendar is a means by which the spi4 link conveys information to the tx data source about the availability of buffer space in the rx fifos that receive data from that data source. a calen- dar is a sequence of status messages that: provides information on the buffer space for a port or traf? ?w. allows user to allocate bandwidth for a port or ?w depending on the overall traf? characteristics. the spi4 status channel operates at 1/8th the spi4 data rate, which is reasonable because data is always sent in 16-byte bursts. thus, the fastest status update can be expected once in every 8 data clock cycles. for a given port, the frequency with which its status is reported to the far-end transmitter source depends on the allocated band- width for the port. it is imperative that the transmitter and receiver devices are programmed with identical calendar sequences. the following examples illustrate this: suppose a channelized sts-48 has three sts-12 ports and four sts-3 ports (channels), each sts-12 port should have four times the bandwidth of an sts-3 port and 12 times the bandwidth of an sts-1 port within a single calendar cycle. the ?st step is to map each port to an 8-bit port id (address) as shown in table 23 table 10. port id mapping the calendar sequence is as follows: a1, a2, a3, b1, a1, a2, a3, b2, a1, a2, a3, b3, a1, a2, a3, b4 the number of calendar entries is thus 16. this calendar sequence is programmed in the transmit calendar mem- ory as follows: this example uses the main calendar. the calendar memory is selected by setting the tx_cal_mem_sel bit (address 30917 in spia and address 30a17 in spib) to ?? writes are done to addresses 0x31000 - 0x3100f. this will correspond to entries 0x00 - 0x0f in the calendar memory. this is shown in table 11. note that the main calendar memory has 1023 locations and can be pro- grammed through addresses 0x31000 - 0x313fe. the shadow calendar memory also has 1023 locations and can be programmed through addresses 0x31400 - 0x317fe. after programming the calendar memory, the tx_cal_mem_sel bit is set to ?? the calendar length register tx_cal_len_main is set to 16 (address 30922 and 30923 in spia, 30a22 and 30a23 in spib). port bandwidth 8-bit port id (port address) a1 sts-12 0x00 a2 sts-12 0x01 a3 sts-12 0x02 b1 sts-3 0x03 b2 sts-3 0x04 b3 sts-3 0x05 b4 sts-3 0x06 lattice semiconductor orca orspi4 data sheet 58 1036-pin ftsbga devices have been discontinued. tx_cal_m_main (address 30921 in spia and 30a21 in spib) is set to the number of times the calendar sequence needs to be repeated between framing patterns. the shadow calendar can be programmed in the same identical fashion as the main calendar using the steps described above. to enable hitless switching between main and shadow calendar memories, the tx_cal_sw_en bit (address 30916 in spia and 30a16 in spib) should be set to ?? this will cause the transmit status logic to detect the calen- dar select word after the framing pattern. a ?1 detected on the calendar select word selects the main calendar. a ?0 on the calendar select word selects the shadow calendar. it is important to enable this feature in the receive device on the other end of the spi4 link. if the receive device is a lattice orspi4 device, this is done by setting rx_cal_sw_en bit (address 30916 in spia and 30a16 in spib) to ?? this will cause the far-end receive status logic to insert the calendar select word after the framing pattern. table 11. transmit calendar memory contents min_burst_mode the number of transmitted data bytes in a given port s spi-4 data segment can be programmed by setting the burst_val for a given port in the port descriptor memory. in general, setting a port s burst_val will result in transmitted data segments of length (16 * burst_val) bytes. however, data segments shorter than (16 * burst_val) bytes will occur about 15% of the time. there are three reasons for shorter data segments: 1. end-of-packet (eop) causes segment to terminate 2. insuf?ient data is written into a port s transmit fifo to support a full data burst. 3. orspi4 core logic causes occasional short segments. reason 1 will always naturally occur with any spi4 link and so can never be completely eliminated. however, the following steps which take advantage of the min_burst_mode will eliminate short data segments caused by reasons 2 and 3: 1. set min_burst_mode (address 30916, bit 3 for spia and 30a16, bit 3 for spib) to 1. tx calendar memory address tx calendar memory contents (port id) port number 0x00 0x00 a1 0x01 0x01 a2 0x02 0x02 a3 0x03 0x03 b1 0x04 0x00 a1 0x05 0x01 a2 0x06 0x02 a3 0x07 0x04 b2 0x08 0x00 a1 0x09 0x01 a2 0x0a 0x02 a3 0x0b 0x05 b3 0x0c 0x00 a1 0x0d 0x01 a2 0x0e 0x02 a3 0x0f 0x06 b4 lattice semiconductor orca orspi4 data sheet 59 1036-pin ftsbga devices have been discontinued. 2. it is recommended that burst_val for all ports be set to the same value equal to (data_burst_value/16). for example, for a data burst requirement of 64 bytes, all port burst_val should be set to 4. for a data burst require- ment of 128 bytes, all port burst_val should be set to 8. a maximum burst_val of 15 will support a data burst of 240 bytes. having a common burst_val for all ports simpli?s design of the sequencer needed to keep all transmit ports ?led suf?iently at all times for data bursts. with all port burst_val the same, relative port band- width can be set by loading the transmit calendar appropriately. 3. set tx_fifo_threshold_l (address 30945, bits [0:2] for spia, address 30a45, bits [0:2] for spib) to [inte- ger(burst_val/4) + 1]. for example, if burst_val = 10, tx_fifo_threshold_l should be set to 3. 4. set maxburst1 and maxburst2 to integer multiples of burst_val that are at least 2 times burst_val. for example, if burst_val = 4, then maxburst1 could be set to 12 and maxburst2 could be set to 8. to optimize a port for minimum bursts it is best to set maxburst1 and maxburst2 to as high a value as possible. the reason for this is as follows. whenever the transmitter detects a satified status condition when polling a port, that port s credit ?ld (stored in the port descriptor memory) is automatically decremented by burst_val. if the credit ?ld ever drops below burst_val, the port poll will terminate, reducing the available time to ?l the transmit fifos for data bursts. therefore, it is recommended that the spi[a,b]_k_stat signal from the core be monitored and writing be sus- pended to any port whose receive fifo is satisfied. writing to that port can commence once hungry or starving appears at the spi[a,b]_k_stat because this will guarantee that the credit ?ld for the port has been updated to a value greater than burst_val. maximizing the values of maxburst1 and maxburst2 gives the greatest time between credit update and potential decrement below burst_val (which will eventually happen if enough satisfied status conditions occur). this in turn simpli?s the design of a transmit fifo data write state machine. 5. in order to ensure that a full burst_val block of data is always available when a port is serviced, it is neces- sary to synchronize the writing of data to each port s transmit fifo to the transmitter s fifo read sequence. this can be done by monitoring the port_id of the currently serviced spi4 port (spi[a,b]_k_port_id). figure 21, figure 22, and figure 23 show write sequencing that would result in suf?iently full transmit fifos for full data bursts at all times (except for end-of-packet) for 32-bit, 64-bit, and 128-bit aggregation modes respectively. the ?- ures illustrate the most stringent polling sequencing that would still allow consistently full data bursts. for example, the minimum required gap between polls of the same port is determined by the aggregation mode chosen. longer gaps between epeated port polling will result in more ?xibility in timing the transmit fifo writes. the examples in figure 21, figure 22, and figure 23 illustrate a burst_val of 4, but are extendable to burst_val values from 2 to 15. note that burst_val for each port is available on spi[a,b]_k_burst_val. this may be useful in cases where burst_val has not been set to the same value for each port. lattice semiconductor orca orspi4 data sheet 60 1036-pin ftsbga devices have been discontinued. figure 21. write synchronization sequence for 32-bit mode transmit calendar minimum port gap for 32-bit mode . . port 0 port 1 port 2 port 3 port 0 . . minimum separation between repeating port numbers in transmit calendar = 4 for 32-bit mode to allow time to load transmit fifos for data bursts of any length each port in a minimum separation must be located in a different bank set equal burst_val for all ports 32-bit mode (burst_val = 4 example) spi[a,b]_k_clk_j port 0 port 1 port 2 port 3 port 0 . . . 1 port duration = burst_val clock cycles end last write no later than 2 clock cycles before end of port cycle* start 1 st write no sooner than 6 clock cycles before beginning of initial port cycle* end of data burst read for port 0 . . . * rules valid for any value of burst_val in 32-bit mode . . . spi[a,b]_k_port_id range for transmit fifo writes port 0, write 1 port 0, write 2 port 0, write 3 port 0, write 4 conditions for writing to transmit fifo: 1. if burst_val worth of data is ready to be transmitted and 2. port status is not satisfied and 3. within valid time to load port?s transmit fifo as shown above then ok to load transmit fifo with burst_val of data for that port lattice semiconductor orca orspi4 data sheet 61 1036-pin ftsbga devices have been discontinued. figure 22. write synchronization sequence for 64-bit mode port 0 port 1 port 0 . . . 64-bit mode (burst_val = 4 example) 1 port duration = burst_val clock cycles end last write no later than 2 clock cycles before end of port cycle* start 1 st write no sooner than 4 clock cycles before beginning of initial port cycle* port 0, write 4 . . . spi[a,b]_k_clk_j spi[a,b]_k_port_id * rules valid for any value of burst_val in 64-bit mode port 0, write 1 port 0, write 2 port 0, write 3 . . . end of data burst read for port 0 range for transmit fifo writes minimum separation between repeating port numbers in transmit calendar = 2 for 64-bit mode to allow time to load transmit fifos for data bursts of any length both ports in a minimum separation must be located in a different bank transmit calendar minimum port gap for 64-bit mode . . port 0 port 1 port 0 . . set equal burst_val for all ports conditions for writing to transmit fifo: 1. if burst_val worth of data is ready to be transmitted and 2. port status is not satisfied and 3. within valid time to load port?s transmit fifo as shown above then ok to load transmit fifo with burst_val of data for that port lattice semiconductor orca orspi4 data sheet 62 1036-pin ftsbga devices have been discontinued. figure 23. write synchronization sequence for 128-bit mode port 0 port 0 . . . transmit calendar minimum port gap for 128-bit mode . . port 0 port 0 . . 128-bit mode allows for consecutive port polling for any value of burst_val 128-bit mode (burst_val = 4 example) 1 port duration = burst_val clock cycles end last write no later than 2 clock cycles before end of port cycle* start 1 st write no sooner than 3 clock cycles before beginning of initial port cycle* port 0, write 4 . . . spi[a,b]_k_clk_j spi[a,b]_k_port_id * rules valid for any value of burst_val in 128-bit mode . . . port 0, write 3 port 0, write 2 port 0, write 1 end of data burst read for port 0 range for transmit fifo writes conditions for writing to transmit fifo: 1. if burst_val worth of data is ready to be transmitted and 2. port status is not satisfied and 3. within valid time to load port?s transmit fifo as shown above then ok to load transmit fifo with burst_val of data for that port lattice semiconductor orca orspi4 data sheet 63 1036-pin ftsbga devices have been discontinued. 6. in order to avoid straddling packets during a data burst, it is necessary to track the location of an end-of- packet(eop) within a data burst to insert a dummy word whenever the eop does not occur within the ?al 128-bit (16-byte) word of a data burst. if an eop does not occur during the ?al 128-bit word of a data burst, then the user must insert a dummy word with the packet error indicator (spi[a,b]_k_err_j) set to 1 and the end of packet indi- cator (spi[a,b]_k_eop_j) set to 0. during the dummy write, all byte enables (spi[a,b]_k_be_j) should be set to 1 and input data can be set to anything (don? care). examples of the placement of the dummy write in relation to the eop are shown in figure 24, figure 25, and figure 26. figure 24. dummy write requirement for min_burst_mode (128-bit mode) dummy write eop if eop occurs in any write except last write for a given burst_val, must include 1 dummy write before terminating writes for the port dummy write: spi[a,b]_tx128_err = 1 spi[a,b]_tx128_eop = 0 spi[a,b]_tx128_be[15:0] = 0xffff spi[a,b]_tx128_data = don?t care burst_val = n 1 2 n-1 n 128-bit eop ok n-2 n-3 if eop occurs in last write as defined by the burst_val, then no dummy write is required . . . lattice semiconductor orca orspi4 data sheet 64 1036-pin ftsbga devices have been discontinued. figure 25. dummy write requirement for min_burst_mode (64-bit mode) if eop occurs in any write except last two writes for a given burst_val, must include 1 dummy write before terminating writes for the port eop 1 2 n 64-bit eop ok n-2 64-bit dummy write n-1 eop ok . . . dummy write: spi[a,b]_tx64_err_j = 1 spi[a,b]_tx64_eop_j = 0 spi[a,b]_tx64_be_j(7:0) = 0xff spi[a,b]_tx64_data = don?t care if eop occurs in last two writes as defined by the burst_val, then no dummy write is required burst_val = n lattice semiconductor orca orspi4 data sheet 65 1036-pin ftsbga devices have been discontinued. figure 26. dummy write requirement for min_burst_mode (32-bit mode) spi4 fpga/embedded core timing delays when designing application logic within the fpga to interface with the embedded core, it is important to consider the input setup and hold time requirements of the embedded core logic. there are two directions for signaling infor- mation between the fpga and the embedded core. the ?st is where the fpga sources transmit data and associ- ated control signals into the embedded core. data in this direction is always synchronous to the clock source within the fpga. the other data path direction is used to convey calendar port and status information from the embed- ded core to the fpga. all signals in this category are synchronous to the buffered reference clock within the embedded core. all timing is handled in the isplever software using frequency preferences on the associated clocks. if eop occurs in any write except last four writes for a given burst_val, must include 1 dummy write before terminating writes for the port dummy write: spi[a,b]_tx32_err_j = 1 spi[a,b]_tx32_eop_j = 0 spi[a,b]_tx32_be_j(3:0) = 0xf spi[a,b]_tx32_data = don?t care burst_val = n 1 2 n 32-bit eop ok n-2 if eop occurs in last four writes as defined by the burst_val, then no dummy write is required dummy write n-1 eop ok 32-bit 32-bit 32-bit . . . eop eop ok eop ok lattice semiconductor orca orspi4 data sheet 66 1036-pin ftsbga devices have been discontinued. fpga sourced data and control in this mode, the fpga sends data into the embedded core relative to the rising edge of it s own clock as well as providing the clock for the embedded core. the embedded core uses the fpga clock to register all input data and control signals. figure 27 shows the worst case slow and worst case fast propagation delays for the fpga input data and control signals as well as the clock signal. for guaranteed performance it is important that all input signals from the fpga be registered before being sent into the embedded core. clocking schemes and timing diagrams - transmit dpram interface figure 27. data: spi[a,b]_data/sop/eop/be/err/port/we/addr/spi[a,b]_txk_wd_cnt_rst /link_dis clock: spi[a,b]_k_clk_[3:0]; k=32, 64,128 embedded core sourced status the embedded core sources port and status information relative to a buffered version of the externally provided ref- erence clock (trefclk). the fpga receives both the status information and clock, and can use the provided clock to synchronize all status information for it s own use. figure 28 shows the worst case slow and worst case fast propagation delays for the embedded core output status signals as well as the clock signal. with the given timing delays the fpga logic can either immediately register the provided status information or, if required, implement some combinatorial logic function before registering the information. q 3.5/0.5 ns 1.5/0.5 ns d 4.81 / 1.18 ns fpga embedded core c 1.36/ 0.47 ns d1 setup = 2.6 ns hold = - 0.32 ns note: delays represent average max/min values, not absolute values delay delay buffer delay actual delay values are used by isplever lattice semiconductor orca orspi4 data sheet 67 1036-pin ftsbga devices have been discontinued. figure 28. data: atx_portid[7:0], btx_portid[7:0], atx_stat[1:0], btx_stat[1:0], aburst_val[3:0], bburst_val[3:0] clock: atrefclk, btrefclk spi4 transmit software interface the spi4 transmit interface is con?urable through a system bus interface incorporated within the embedded core. the user can gain access to the system bus either through the integrated mpi interface, or through fpga resources using the system bus master/slave interface. please refer to the appropriate lattice semiconductor data sheets and application notes for more information regarding these interfaces. the transmit spi4 interface logic incorporates many con?urable control registers, as well as interrupt and status registers to monitor spi4 performance. table 47 provides a memory map and description of each register within the transmit portion of the spi4 embedded core. special operating modes quarter-rate mode the orspi4 spi4 tx interface is designed to operate at data rates much lower than 622 mbps. even though the oif standard speci?s a minimum data rate of 622 mbits/s, the lower data rates are provided for users who wish to use the spi4 link for applications supporting <10 gbits/s aggregate bandwidth (sts-48, sts-3, gb ethernet, etc.). to enable this low speed mode, user should set the software register bit spi4_quarter_rate (address 30915 in spia and 30a15 in spib) to ?? this supports data rates in the range of 100 - 200 mbps. note that the normal operating modes 32-bit, 64-bit and 128-bit are independent of the quarter-rate mode. in quarter-rate mode, the transmit pll is held in reset by setting the mreset hardware pin to ?? the pll bypass mode is enabled by set- ting the bypass pin to ? which causes the spi[a,b]_trefclk_x8 clock from the fpga to be used as the trans- mit reference clock. it must be two- times the desired transmit spi4 line clock rate. when not operating the transmit spi4 core in quarter-rate mode, this signal should be tied off. ex: for a 100 mhz transmit spi4 line clock, spia_trefclk_x8 from the fpga must be 200 mhz. d 3.5/0.5 ns 4.0/1.0 ns d 5.4 / 2.1 ns fpga embedded core c 1.36/ 0.47 ns d delay (includes ck to q) clock insertion trefclk (from off-chip) atrefck_f btrefclk_f delay = 6.8 / 2.4 ns q note: delays represent average max/min values, not absolute values actual delay values are used by isplever buffer delay clock buffer delay relative to data lattice semiconductor orca orspi4 data sheet 68 1036-pin ftsbga devices have been discontinued. orspi4 spi4 receive path functional description this section describes the receive section of the spi4 interface. although there will be two spi4 compliant inter- faces within the fpsc, this section describes a single interface. the other interface is a duplicate and therefore needs no additional technical description. orspi4 receive features the receive spi4 interface supports the following features: 10 gbits/s data throughput. four dual-port memory banks supporting buffering for up to 32 ports. if support for more than 32 ports is needed, then the dual-port memories can be used for clock domain crossing purposes and data can be buffered in an external memory. port status sequencer (pss), including receive calendar (main and shadow), will support up to 256 ports, the maximum number of ports supported by the spi4 standard. 32, 64 and 128-bit data width aggregation modes at the user (core/fpga) interface. programmable main and shadow calendar table. all calendar con?uration parameters speci?d in the spi4 standard such as calendar_len, calendar_m are supported. optional dynamic alignment of receive data at the high-speed spi4 interface. dynamic alignment is required at rates > 700 mbits/s (350 mhz). the spi4 receive logic enables users to read incoming port data using a variety of interfaces and associated clock domain options. it uses dual port rams (dpram) for temporary storage and clock domain crossing. data is received in spi4 format as lvds signals at the receive interface. the data is written into dpram as received and read from the dprams as requested by the fpga logic. fifo status is transmitted from the receive status inter- face according to a pre-con?ured polling sequence contained within the receive calendar. data is formatted into the spi4 receive status format and sent to the physical links as either lvds or lvttl signals. there are also several other features incorporated into the embedded core such as parallel loopback and far end loopback to assist in debugging and statistic gathering. these features, and the spi4 data formats and initialization procedures are documented in separate sections since they involve both the transmit and receive paths. the major blocks associated with the orspi4 receiver are: spi4 receive logic - data spi4 receive data input (rdi) block spi4 receive data protocol (rdp) logic data formatter address map dpram banks port status sequencer logic (pss) spi4 receive logic - status spi4 receive status protocol (rsp) logic spi4 receive status output (rso) block lattice semiconductor orca orspi4 data sheet 69 1036-pin ftsbga devices have been discontinued. these blocks will be described in detail in the following sections. the orspi4 receive functional block diagram is shown in figure 29. figure 29. orspi4 receive functional block diagram orspi4 receive functional block overview the orspi4 high-speed receive logic receives high-speed data on 16 lvds pairs (rdat[15:0]), control on one lvds pair (rctl) and clock on one lvds pair (rdclk) at the spi4 interface. this is an oif-spi-4 02.0 compliant interface that supports data rates in the range of 622-900 mbps. additionally lower-speed data in the range of 100- 200 mbps is also supported. the high-speed receive interface logic supports both static and dynamic alignment as speci?d by the oif-spi-4 02.0 speci?ation. dynamic alignment allows for +/- one bit period of skew. during dynamic alignment, training patterns are detected and deskew performed. data is then deserialized into 128-bit data and 8-bit control bus. the spi4 receive data protocol logic then extracts the control information such as port_id, sop, eop and err into a separate sideband bus while still preserving wire-speed throughput. data and control signals are then written into one of four dual-port rams (dprams). per-port buffering is supported for a maximum of 32 ports. the dprams are built as multiple virtual fifos where each fifo can be allocated for a port by the user through software. at the fpga fabric, the user reads data for the desired ports from the fifos [a,b]rstat [a,b]rsclk rx dpram spi[a,b]_k_data_j, be_j spi[a,b]_k_sopj, eopj, errj [a,b]stop_on_eopj spi[a,b]_k_rd_j spi[a,b]_k_addr_j address spi[a,b]_k_clk_j mapper rdi [a,b]rdat [a,b]rctl [a,b]rdclk pss rsp rso spi[a,b]_k_stat spi[a,b]_k_port_id spi[a,b]_k_ext_stat_en spi[a,b]_k_pss_we spi[a,b]_k_pss_clk rlstat rlsclk 16 2 2 2 8 3 3 rdp data control control data control fpga interface spi[a,b]_k_fifo_empty_j k = 32, 64 or 128 j= 0, 1, 2 or 3 spi[a,b]_k_ ctl_j (32 and 64 only) [a,b]rlsclk_f lattice semiconductor orca orspi4 data sheet 70 1036-pin ftsbga devices have been discontinued. based on the empty status signals presented from the fifos. the user can select a 32-bit, 64-bit or 128-bit wide fifo interface depending on the fpga design requirements. there are two spi4 cores in the orspi4 device. they are referenced in the document as spia and spib respec- tively. orspi4 receive embedded core/fpga interface description orspi4 receive i/o modes the fpga interface i/os to the orspi4 logic block vary depending on the operating modes. there are three main user operating modes: 32-bit operating mode: each of the four dprams can be con?ured with a 32-bit user data plus controls across the fpga interface. this mode is particularly useful if the user is aggregating multiple 32-bit interfaces into a sin- gle spi4 interface. 64-bit operating mode: a dpram pair can be con?ured with 64-bit user data bus plus controls across the fpga interface. two such dpram pairs are available. more ?xibility is provided by con?uring one pair of dpram banks in 64-bit mode and the remaining two banks in 32-bit mode. 128-bit operating mode: all four dpram banks are aggregated into a single fifo with a 128-bit user data inter- face. several other features are: ability to pause for two clock cycles when an eop is detected using the astop_on_eop (spia) or bstop_on_eop (spib) control signal. please refer to the timing diagrams for detailed information. table 12 lists i/os for spia core only. they are identical in the spib core as well. table 12. spia core receive fpga interface in 32-bit mode dpram fpga interface i/os direction from/to description 0 spia_rx32_addr_0[2:0] fpga core fifo read address. spia_rx32_data_0[31:0] core fpga fifo read data. spia_rx32_be_0[3:0] core fpga byte enables bit 3 - byte enable for spia_rx32_data_0[31:24] bit 2 - byte enable for spia_rx32_data_0[23:16] bit 1 - byte enable for spia_rx32_data_0[15:8] bit 0 - byte enable for spia_rx32_data_0[7:0] spia_rx32_ctl_0 core fpga port id indicator. a ? indicates that the spia_rx32_data_0 bus contains the port id. spia_rx32_sop_0 core fpga start of packet indicator. a ? indicates start of packet. spia_rx32_eop_0 core fpga end of packet indicator. a ? indicates end of packet. spia_rx32_err_0 core fpga error. a ? indicates an error in the current word. spia_rx32_fifo_empty_0 core fpga fifo empty ?g. depends on the rx_dpram_empty_type_sela[0] software register bit in address 0x30920. when this bit is set to ?? (default) the empty ?g indicates truly empty. when this bit is set to ?? the empty ?g indicates that the fifo is 1/4 full - 1. astop_on_eop0 fpga core timing control for handling end of packet. spia_rx32_clk_0 fpga core fifo read clock. spia_rx32_rd_0 fpga core fifo read enable. note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 71 1036-pin ftsbga devices have been discontinued. 1 spia_rx32_addr_1[2:0] fpga core fifo read address. spia_rx32_data_1[31:0] core fpga fifo read data. spia_rx32_be_1[3:0] core fpga byte enables bit 3 - byte enable for spia_rx32_data_1[31:24] bit 2 - byte enable for spia_rx32_data_1[23:16] bit 1 - byte enable for spia_rx32_data_1[15:8] bit 0 - byte enable for spia_rx32_data_1[7:0] spia_rx32_ctl_1 core fpga port id indicator. a ? indicates that the spia_rx32_data_1 bus contains the port id. spia_rx32_sop_1 core fpga start of packet indicator. a ? indicates start of packet. spia_rx32_eop_1 core fpga end of packet indicator. a ? indicates end of packet. spia_rx32_err_1 core fpga error. a ? indicates an error in the current word. spia_rx32_fifo_empty_1 core fpga fifo empty ?g. depends on the rx_dpram_empty_type_sela[1] software register bit in address 0x30920. when this bit is set to ?? (default) the empty ?g indicates truly empty. when this bit is set to ?? the empty ag indicates that the fifo is 1/4 full -1. astop_on_eop1 fpga core timing control for handling end of packet. spia_rx32_clk_1 fpga core fifo read clock. spia_rx32_rd_1 fpga core fifo read enable. 2 spia_rx32_addr_2[2:0] fpga core fifo read address. spia_rx32_data_2[31:0] core fpga fifo read data. spia_rx32_be_2[3:0] core fpga byte enables bit 3 - byte enable for spia_rx32_data_2[31:24] bit 2 - byte enable for spia_rx32_data_2[23:16] bit 1 - byte enable for spia_rx32_data_2[15:8] bit 0 - byte enable for spia_rx32_data_2[7:0] spia_rx32_ctl_2 core fpga port id indicator. a ? indicates that the spia_rx32_data_2 bus contains the port id. spia_rx32_sop_2 core fpga start of packet indicator. a ? indicates start of packet. spia_rx32_eop_2 core fpga end of packet indicator. a ? indicates end of packet. spia_rx32_err_2 core fpga error. a ? indicates an error in the current word. spia_rx32_fifo_empty_2 core fpga fifo empty ?g. depends on the rx_dpram_empty_type_sela[2] software register bit in address 0x30920. when this bit is set to ?? (default) the empty ?g indicates truly empty. when this bit is set to ?? the empty ag indicates that the fifo is 1/4 full -1. astop_on_eop2 fpga core timing control for handling end of packet. spia_rx32_clk_2 fpga core fifo read clock. spia_rx32_rd_2 fpga core fifo read enable. table 12. spia core receive fpga interface in 32-bit mode (continued) dpram fpga interface i/os direction from/to description note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 72 1036-pin ftsbga devices have been discontinued. 3 spia_rx32_addr_3[2:0] fpga core fifo read address. spia_rx32_data_3[31:0] core fpga fifo read data. spia_rx32_be_3[3:0] core fpga byte enables bit 3 - byte enable for spia_rx32_data_3[31:24] bit 2 - byte enable for spia_rx32_data_3[23:16] bit 1 - byte enable for spia_rx32_data_3[15:8] bit 0 - byte enable for spia_rx32_data_3[7:0] spia_rx32_ctl_3 core fpga port id indicator. a ? indicates that the spia_rx32_data_3 bus contains the port id. spia_rx32_sop_3 core fpga start of packet indicator. a ? indicates start of packet. spia_rx32_eop_3 core fpga end of packet indicator. a ? indicates end of packet. spia_rx32_err_3 core fpga error. a ? indicates an error in the current word. spia_rx32_fifo_empty_3 core fpga fifo empty ?g. depends on the rx_dpram_empty_type_sela[3] software register bit in address 0x30920. when this bit is set to ?? (default) the empty ?g indicates truly empty. when this bit is set to ?? the empty ag indicates that the fifo is 1/4 full -1. astop_on_eop3 fpga core timing control for handling end of packet. spia_rx32_clk_3 fpga core fifo read clock. spia_rx32_rd_3 fpga core fifo read enable. status i/os spia_rx32_port_id[7:0] fpga core port id used by the core as write address into the status ram. spia_rx32_stat[1:0] fpga core port status corresponding to spia_rx32_port_id spia_rx32_ext_stat_en fpga core when set to ?? the status from spia_rx32_stat will be sent on the spi4 status i/f. spia_rx32_pss_we fpga core write enable to the internal status ram. spia_rx32_pss_clk fpga core write clock to the internal status ram. misc. i/os spi_datm_a fpga core valid only during static data capture. should be set to ? in dynamic align- ment mode. ? - bypass delay line circuit on the clock (ardclk) path. ? - enables delay line circuit on the ardclk path. spi_dlytap_a[2:0] fpga core these bits control the effective delay of the delay line circuit on the ard- clk path. valid values are from 0-6. arlsclk_f core fpga internal clock (ardclk/4) used to clock all receive status logic. table 12. spia core receive fpga interface in 32-bit mode (continued) dpram fpga interface i/os direction from/to description note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 73 1036-pin ftsbga devices have been discontinued. table 13. spia core receive fpga interface in 64-bit mode dpram fpga interface i/os direction from/to description 0 spia_rx64_addr_0[2:0] fpga core fifo read address. spia_rx64_data_0[63:0] core fpga fifo read data. spia_rx64_be_0[7:0] core fpga byte enables bit 7 - byte enable for spia_rx64_data_0[63:56] bit 6 - byte enable for spia_rx64_data_0[55:48] bit 5 - byte enable for spia_rx64_data_0[47:40] bit 4 - byte enable for spia_rx64_data_0[39:32] bit 3 - byte enable for spia_rx64_data_0[31:24] bit 2 - byte enable for spia_rx64_data_0[23:16] bit 1 - byte enable for spia_rx64_data_0[15:8] bit 0 - byte enable for spia_rx64_data_0[7:0] spia_rx64_ctl_0 core fpga port id indicator. a ? indicates that the spia_rx64_data_0 bus contains the port id. spia_rx64_sop_0 core fpga start of packet indicator. a ? indicates start of packet. spia_rx64_eop_0 core fpga end of packet indicator. a ? indicates end of packet. spia_rx64_err_0 core fpga error. a ? indicates an error in the current word. spia_rx64_fifo_empty_0 core fpga fifo empty ?g. depends on the rx_dpram_empty_type_sela[0] software register bit in address 0x30920. when this bit is set to ?? (default) the empty ?g indicates truly empty. when this bit is set to ?? the empty ag indicates that the fifo is 1/4 full -1. astop_on_eop0 fpga core timing control for handling end of packet. spia_rx64_clk_0 fpga core fifo read clock. spia_rx64_rd_0 fpga core fifo read enable. 1 spia_rx64_addr_1[2:0] fpga core fifo read address. spia_rx64_data_1[63:0] core fpga fifo read data. spia_rx64_be_1[7:0] core fpga byte enables bit 7 - byte enable for spia_rx64_data_1[63:56] bit 6 - byte enable for spia_rx64_data_1[55:48] bit 5 - byte enable for spia_rx64_data_1[47:40] bit 4 - byte enable for spia_rx64_data_1[39:32] bit 3 - byte enable for spia_rx64_data_1[31:24] bit 2 - byte enable for spia_rx64_data_1[23:16] bit 1 - byte enable for spia_rx64_data_1[15:8] bit 0 - byte enable for spia_rx64_data_1[7:0] spia_rx64_ctl_1 core fpga port id indicator. a ? indicates that the spia_rx64_data_1 bus contains the port id. spia_rx64_sop_1 core fpga start of packet indicator. a ? indicates start of packet. spia_rx64_eop_1 core fpga end of packet indicator. a ? indicates end of packet. spia_rx64_err_1 core fpga error. a ? indicates an error in the current word. spia_rx64_fifo_empty_1 core fpga fifo empty ?g. depends on the rx_dpram_empty_type_sela[0] software register bit in address 0x30920. when this bit is set to ?? (default) the empty ?g indicates truly empty. when this bit is set to ?? the empty ag indicates that the fifo is 1/4 full -1. astop_on_eop1 fpga core timing control for handling end of packet. spia_rx64_clk_1 fpga core fifo read clock. spia_rx64_rd_1 fpga core fifo read enable. note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 74 1036-pin ftsbga devices have been discontinued. status i/os spia_rx64_port_id[7:0] fpga core port id used by the core as write address into the status ram. spia_rx64_stat[1:0] fpga core port status corresponding to spia_rx64_port_id spia_rx64_ext_stat_en fpga core when set to ?? the status from spia_rx64_stat will be sent on the spi4 status i/f. spia_rx64_pss_we fpga core write enable to the internal status ram. spia_rx64_pss_clk fpga core write clock to the internal status ram. misc. i/os spi_datm_a fpga core valid only during static data capture. should be set to ? in dynamic align- ment mode. ? - bypass delay line circuit on the clock (ardclk) path. ? - enables delay line circuit on the ardclk path. spi_dlytap_a[2:0] fpga core these bits control the effective delay of the delay line circuit on the ard- clk path. valid values are from 0-6. arlsclk_f core fpga internal clock (ardclk/4) used to clock all receive status logic. table 13. spia core receive fpga interface in 64-bit mode (continued) dpram fpga interface i/os direction from/to description note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 75 1036-pin ftsbga devices have been discontinued. spi4 receive logic blocks - detailed description rdi block the spi4 high-speed receive data input (rdi) block contains the high-speed receive logic for the spi4 block. incoming lvds signals, in spi4 format, include the 16-bit data bus (rdat[15:0]), a control bit (rctl) and a source table 14. spia core receive fpga interface in 128-bit mode dpram fpga interface i/os direction from/to description 0 spia_rx128_addr[2:0] fpga core fifo read address. spia_rx128_data[127:0] core fpga fifo read data. spia_rx128_be[15:0] core fpga byte enables bit 15- byte enable for spia_rx128_data[127:120] bit 14- byte enable for spia_rx128_data[119:112] bit 13- byte enable for spia_rx128_data[111:104] bit 12- byte enable for spia_rx128_data[103:96] bit 11- byte enable for spia_rx128_data[95:88] bit 10- byte enable for spia_rx128_data[87:80] bit 9- byte enable for spia_rx128_data[79:72] bit 8- byte enable for spia_rx128_data[71:64] bit 7 - byte enable for spia_rx128_data[63:56] bit 6 - byte enable for spia_rx128_data[55:48] bit 5 - byte enable for spia_rx128_data[47:40] bit 4 - byte enable for spia_rx128_data[39:32] bit 3 - byte enable for spia_rx128_data[31:24] bit 2 - byte enable for spia_rx128_data[23:16] bit 1 - byte enable for spia_rx128_data[15:8] bit 0 - byte enable for spia_rx128_data[7:0] spia_rx128_portid[7:0] core fpga port id for the current data. spia_rx128_sop core fpga start of packet indicator. a ? indicates start of packet. spia_rx128_eop core fpga end of packet indicator. a ? indicates end of packet. spia_rx128_err core fpga error. a ? indicates an error in the current word. spia_rx128_fifo_empty core fpga fifo empty ?g. depends on the rx_dpram_empty_type_sela[0] software register bit in address 0x30920. when this bit is set to ?? (default) the empty ?g indicates truly empty. when this bit is set to ?? the empty ag indicates that the fifo is 1/4 full -1. astop_on_eop fpga core timing control for handling end of packet. spia_rx128_clk fpga core fifo read clock. spia_rx128_rd fpga core fifo read enable. spia_rx128_port_id[7:0] fpga core port id used by the core as write address into the status ram. spia_rx128_stat[1:0] fpga core port status corresponding to spia_rx128_port_id spia_rx128_ext_stat_en fpga core when set to ?? the status from spia_rx128_stat will be sent on the spi4 status i/f. spia_rx128_pss_we fpga core write enable to the internal status ram. spia_rx128_pss_clk fpga core write clock to the internal status ram. misc. i/os spi_datm_a fpga core valid only during static data capture. should be set to ? in dynamic align- ment mode. ? - bypass delay line circuit on the clock (ardclk) path. ? - enables delay line circuit on the ardclk path. spi_dlytap_a[2:0] fpga core these bits control the effective delay of the delay line circuit on the ard- clk path. valid values are from 0-6. arlsclk_f core fpga internal clock (ardclk/4) used to clock all receive status logic. note: for spib replace a with b lattice semiconductor orca orspi4 data sheet 76 1036-pin ftsbga devices have been discontinued. synchronous ddr clock (rdclk). the 16-bit data bus and control signal are ddr with respect to rdclk. the incoming data is deserialized to a 128-bit format and the control information is converted to an 8-bit format. deseri- alized data, control signals and a low-speed clock, derived from the high-speed rdclk, are forwarded to the pro- tocol (rdp) block. the rdi block alignment logic detects training patterns and perform dynamic alignment of the incoming data. for low speed incoming data at rates up to 700 mbits/s, static alignment can be chosen through a programmable con- trol bit. the low speed mode is described in a later section. at speeds above 700 mb/s (350 mhz), however, it becomes necessary to use dynamic alignment. skews of up to ?one clock period can be compensated for by the dynamic alignment logic, which chooses the best phase of the receive clock, out of 16 possibilities, to center each data bit for the best possible setup/hold margin. the receive dynamic alignment logic periodically samples the data to verify that data can be transferred reliably as temperature and voltage levels in the system vary. it then makes appropriate adjustments as needed. the output from the rdi block is the low speed 128-bit data bus and 8-bit control bus along with a low speed clock which is 1/4th the rate of the spi4 receive clock rdclk. the orspi4 receive high-speed interface also supports static data capture as shown in figure 30. as shown in the ?ure, the key difference that exists between the clock and data paths is the delay line in the clock path. the high- speed loopback works in both static and dynamic alignment modes. the delay line circuit is a series of buffers with programmable stages that are controlled through two signals from the fpga - spi_datm_a (spia) or spi_datm_b (spib) and spi_dlytap_a[2:0] (spia) or spi_dlytap_b[2:0] (spib). the object of having pro- grammable delay stages is to delay rdclk appropriately so that both its rising and falling edges hit the data eye with suf?ient setup and hold margin for data capture. various delay settings allow the data to be centered vs. the clock for the best setup and hold margin. for details on programming the orspi4 receiver in static and dynamic capture modes, refer to the section ?tatic capture operating mode? figure 30. static data capture rdp block the spi4 receive data protocol (rdp) block receives data from rdi block and is responsible for decoding the in- band control information while preserving wire-speed throughput. it passes both data and control information, such as link address, sop, eop and error, to the receive dprams. the rdp block also parses the control words embedded within the incoming data. using this control information, it performs the following functions: checks dip-4 parity [a,b]rdat[15:0] [a,b]rdclk lvds buffers lvds buffers from transmit blocks spi4_loopbk_hs dynamic static data clock data clock delay spi_dlytap_[a,b][2:0] spi_datm_[a,b] (controls from fpga) 0 1 0 1 line lattice semiconductor orca orspi4 data sheet 77 1036-pin ftsbga devices have been discontinued. monitors for continuous alignment (if more than a programmable number of dip-4 parity errors exist, there may be an alignment problem). in the event of dip-4 parity errors, instructs the status block to send status framing pattern ?1 on the receive spi4 status bus. removes idle/training words. extracts link address and sop, eop and valid packet (no error) signals. receive dprams there are four dprams referred to as banks 0, 1, 2 and 3. each bank has a 32-bit data interface to the fpga. each dpram has its own individual read enable and read clock allowing it to be read by the fpga application independently. every dpram bank is con?ured by software to operate in one of 32-bit, 64-bit or 128-bit mode. every dpram bank is also con?ured to contain 1, 2, 4 or 8 virtual fifos. the user determines the number of fifos depending on the number of ports and buffer requirements for the ports as required by a given application. the programming of a dpram bank in 32-bit, 64-bit or 128-bit mode and programming of the number of virtual fifos within a dpram bank is done through software as shown in table 18. note that in 64-bit mode, dprams 0 and 1 have to be con?ured identically. the combined dpram pair is referred to as dpram ?? similarly dpram pairs 2 and 3 have to be con?ured identically. this combined dpram pair is referred to as dpram ?? in 128-bit mode, all dprams have to be con?ured identically. the combined dpram banks are collectively referred to as dpram ?? the aggregation modes can be used in ?e possible combinations as shown in table 16. the size of the embedded data and control fifos for each mode is shown in table 17. the user accesses a virtual fifo using the 3-bit fifo read address (refer to table 12, table 13, and table 14) from the fpga. table 15 shows the indexed partition based upon the con?ured dpram partitioning and aggregation mode. in 32-bit operating mode, the user always reads data as four 32-bit word bursts (plus one additional clock cycle to read the port id) unless an eop is received. if an eop occurs and the astop_on_eopj (j=0,1,2,3) or bstop_on_eopj is ?? the core will cease transmission of the remaining words in the burst and start transferring the next set of data. for example, if the eop happens in the second word of a 4-word burst, the core will not pro- vide the remaining two words. instead, it will start bursting the next set of data. the exception is when the astop_on_eopj (j=0,1,2,3) or bstop_on_eopj is asserted. when this signal is ?? the core will pause for 2 clock cycles after an eop. the byte enables (spia_rx32_be_j) are set to ? indicating that the read data is not valid. table 15. fifo address based on programmed virtual fifos fifo address (from fpga) description xxx ignored when a dpram is con?ured to support only one virtual fifo 000 selects fifo 0 when dpram is con?ured to support 2, 4 or 8 virtual fifos 001 selects fifo 1 when dpram is con?ured to support 2, 4 or 8 virtual fifos 010 selects fifo 2 when dpram is con?ured to support 4 or 8 virtual fifos 011 selects fifo 3 when dpram is con?ured to support 4 or 8 virtual fifos 100 selects fifo 4 when dpram is con?ured to support 8 virtual fifos 101 selects fifo 5 when dpram is con?ured to support 8 virtual fifos 110 selects fifo 6 when dpram is con?ured to support 8 virtual fifos 111 selects fifo 7 when dpram is con?ured to support 8 virtual fifos lattice semiconductor orca orspi4 data sheet 78 1036-pin ftsbga devices have been discontinued. table 16. possible combinations of aggregation modes table 17. memory size for each aggregation mode and partitioning mode valid banks 0 to 3 in 32-bit aggregation mode yes banks 0, 1 in 64-bit aggregation mode, banks 2,3 in 64-bit mode ye s banks 0,1 in 64-bit mode, banks 2 & 3 in 32-bit mode ye s banks 0,1 in 32-bit mode, banks 2 & 3 in 64-bit mode ye s all banks in 128-bit yes bank 0 in 32-bit mode, bank 1 in 64-bit mode or vice-versa no bank 2 in 32-bit mode, bank 3 in 64-bit mode or vice-versa no operating mode number of con?ured virtual fifo partitions data fifo depth (in bytes) control fifo depth (in bytes) 32-bit 1 2k 512 2 1k 256 4 512 128 8 256 64 64-bit 1 4 k 1k 2 2 k 512 4 1 k 256 8 512 128 128-bit 1 8 k 2k 2 4 k 1k 4 2 k 512 8 1 k 256 lattice semiconductor orca orspi4 data sheet 79 1036-pin ftsbga devices have been discontinued. table 18. register bit settings for aggregation mode and partition size dpram aggregation mode address 30907 (spia), 30a07 (spib) virtual fifo partition size address 30906 (spia), 30a06 (spib) con?uration dpram 0 (register bits 0:1) = 00 register bits 0:1 = 00 32-bit data width, partition size 1 01 32-bit data width, partition size 2 10 32-bit data width, partition size 4 11 32-bit data width, partition size 8 01 00 64-bit data width, partition size 1 01 64-bit data width, partition size 2 10 64-bit data width, partition size 4 11 64-bit data width, partition size 8 10 00 128-bit data width, partition size 1 01 128-bit data width, partition size 2 10 128-bit data width, partition size 4 11 128-bit data width, partition size 8 dpram 1 (register bits 2:3) = 00 register bits 2:3 = 00 32-bit data width, partition size 1 01 32-bit data width, partition size 2 10 32-bit data width, partition size 4 11 32-bit data width, partition size 8 01 00 64-bit data width, partition size 1 01 64-bit data width, partition size 2 10 64-bit data width, partition size 4 11 64-bit data width, partition size 8 10 00 128-bit data width, partition size 1 01 128-bit data width, partition size 2 10 128-bit data width, partition size 4 11 128-bit data width, partition size 8 dpram 2 (register bits 4:5) = 00 register bits 4:5 = 00 32-bit data width, partition size 1 01 32-bit data width, partition size 2 10 32-bit data width, partition size 4 11 32-bit data width, partition size 8 01 00 64-bit data width, partition size 1 01 64-bit data width, partition size 2 10 64-bit data width, partition size 4 11 64-bit data width, partition size 8 lattice semiconductor orca orspi4 data sheet 80 1036-pin ftsbga devices have been discontinued. receive address mapper this control block decodes the port address received from the spi4 rx interface to determine the physical memory address (to access the dpram memories) for that port address. each port address must be mapped to one of the virtual fifos in the dprams. each virtual fifo can be used to buffer data for a single port. since there is a total of four dprams, eight virtual fifos in each dpram provides 32 per-port buffers. the number of per-port buffers varies according to the operating mode. for example, in 32-bit mode, a total of 32 per-port buffers is possible. in 64-bit mode, a total of 16 per-port buffers is provided. in 128-bit mode, a total of eight per-port buffers is provided. to decode the physical memory information, this block accesses a user-con?ured port descriptor memory (pdm) which is simply a look-up-table. the pdm is an embedded memory within the orspi4 core. there is one each for spia and spib cores. since 256 ports can be supported by the device, the pdm has 256 locations. the user indexes this memory using the 8-bit spi4 port id as the software write address into the embedded memory space 31000 - 310ff. for example, a software write into address 31000 con?ures the pdm for port id 0. the software procedure to con?ure the pdm is described below: user has to select the pdm by writing a ? into bit 3 of address 30917 (spia) or 30a17 (spib). subsequent writes to addresses 31000-310ff correspond to entries 0x00-0xff in the pdm. these may be writ- ten in any order. upon completion of the pdm con?uration, the pdm select bit (bit 3 of address 30917 or 30a17) must be set to ?? the contents of the pdm may also be read back. this is done by ?st selecting the pdm memory by writing a ? to bit 3 of address 30917 or 30a17. reads are then done from addresses 31000-310ff. upon completion of the reads, the pdm select bit is set to ?? to allocate a buffer space to a port, the user has to choose one of the four dpram banks (bank_id ?ld in the pdm) and a virtual fifo (partition_id) within the chosen dpram bank. each location in the pdm contains the ?lds described below for each port address. 10 00 128-bit data width, partition size 1 01 128-bit data width, partition size 2 10 128-bit data width, partition size 4 11 128-bit data width, partition size 8 dpram 3 (register bits 6:7) = 00 register bits 6:7 = 00 32-bit data width, partition size 1 01 32-bit data width, partition size 2 10 32-bit data width, partition size 4 11 32-bit data width, partition size 8 01 00 64-bit data width, partition size 1 01 64-bit data width, partition size 2 10 64-bit data width, partition size 4 11 64-bit data width, partition size 8 10 00 128-bit data width, partition size 1 01 128-bit data width, partition size 2 10 128-bit data width, partition size 4 11 128-bit data width, partition size 8 dpram aggregation mode address 30907 (spia), 30a07 (spib) virtual fifo partition size address 30906 (spia), 30a06 (spib) con?uration lattice semiconductor orca orspi4 data sheet 81 1036-pin ftsbga devices have been discontinued. partition address (pa) : this is the least signi?ant 3-bit ?ld [2:0] within a pdm location. this ?ld provides the virtual fifo partition address for each port. each partition is of equal size. there can be a total of 8 virtual fifo partitions within each dpram bank. bank_id : this occupies bits 4:3 within a pdm location. this 2-bit ?ld is used to select one of the four dpram banks to store the received data. the user initially assigns this information by programming the bank_id. legal values for the bank_id depend on the operating mode. in 32-bit mode, the legal values are 0,1,2 and 3. in 64-bit mode, the legal values are 0 and 2. in 64-bit mode, the legal value is only 0. while programming the pdm allocates a buffer for every port (or multiple ports), the buffer sizes themselves are con?ured by the user through software register settings for dpram aggregation mode (address 30907 for spia and 30a07 for spib. refer to table 18) number of virtual fifos in a dpram (address 30906 for spia and 30a06 for spib. refer to table 17). figure 31 shows a block diagram of the port description memory. figure 31. receive address mapper block diagram virtual receive memory fifos (partitions) and port mapping as was the case for the transmit logic, there are up to 32 virtual receive fifo partitioning, 256 port numbers and the receive calendar can contain up to 1023 entries. the user must set up the mapping between the fifo parti- tions and the port number for each active port. the user must also set up the calendar sequence for polling the active ports. the simplest mapping of the read dpram partitions, which support a maximum of 32 ports, is to have a 1:1 map- ping between the fifo partition and the port address. the 1023 depth of the calendar allows for uneven bandwidth allocation across ports where high bandwidth ports can have multiple entries within the calendar table. the read scheduling logic, however, is designed to support up to 256 ports. each port (up to 32 ports) can have its unique buffer. a single port or multiple ports can be assigned to a buffer by con?uring the pdm. the user must, using fpga logic, assure that data is read from the virtual fifo using the same port sequencing that is expected pdm fields 0 255 bank_id pa port descriptor software write memory lattice semiconductor orca orspi4 data sheet 82 1036-pin ftsbga devices have been discontinued. by the calendar. this ensures that the bandwidth allocated for a given port is maintained and the port s fifo is emptied at the same rate that it is being ?led up at the far-end transmitter. for example, if the calendar assumes that the buffer for port 2 is ?led more frequently than the buffer for port 4, then the fpga logic must read the buffer (virtual fifo) for port 2 more frequently than port 4 to ensure that bandwidth requested for port 2 is maintained across the spi4 link. the user also has a choice to not use the per-port buffers and treat the dprams as pure clock-domain crossing fifos. this is done by simply con?uring each dpram in 128-bit mode and setting up the number of virtual fifo partitions to ?? if the user application supports more than 32 ports, multiple ports need to share a buffer or external memory can be used. the orspi4 core provides a qdr-ii sram memory controller for additional buffering. the qdr-ii sram memory was chosen owing to the wire-speed throughput that can be realized through dedicated write and read ports. in this case, the user must implement control logic to sequence external memory reads from the selected vir- tual fifos and the fifos are used only for crossing between clock domains. in many cases a second qdr-ii memory interface is needed, thus a soft ip version of the core is available. suppose there are 6 ports, and each port is mapped to a single buffer or virtual fifo: the ?st step is to decide the aggregation mode and fifo size depending on the bandwidth needed by the port(s). this is shown in table 19. the second step is to con?ure the dprams through software register settings shown in table 20. note that dpram banks 2 and 3 are con?ured identically since they are con?ured to be a 64-bit interface. the last step is to con?ure the pdm using the procedure described in the address mapper section. the con- tents of the pdm are shown in table 21. table 19. dpram con?uration example table 20. dpram software register settings example table 21. pdm contents example dpram bank aggregation mode number of virtual fifos virtual fifo size (bytes) 0 32-bit 2 1k 1 32-bit 2 1k 2,3 64-bit 2 2k dpram bank aggregation mode number of virtual fifos 0 rx_dpram_0_aggr_mode = 00 rx_dpram_0_numfifo = 01 1 rx_dpram_1_aggr_mode = 00 rx_dpram_0_numfifo = 01 2 rx_dpram_2_aggr_mode = 01 rx_dpram_0_numfifo = 01 3 rx_dpram_3_aggr_mode = 01 rx_dpram_0_numfifo = 01 port id bank id partition address 0x00 00 000 0x01 001 0x02 01 000 0x03 001 0x04 10 000 0x05 001 lattice semiconductor orca orspi4 data sheet 83 1036-pin ftsbga devices have been discontinued. port status sequencer (pss) logic in addition to formatting received data and sending it to the fpga logic, the receive block also sends status infor- mation to the spi4 status interface. the port status sequencer (pss) block is responsible for providing port status to the spi4 receive status protocol block (rsp) according to a pre-con?ured calendar sequence. status is derived from the ?l-levels of the dpram fifos and/or from the fpga status interface. when status is provided by fpga logic, the fpga application writes status information to a 256 word pss memory in a random fashion. the pss memory is addressed by an 8-bit port id (spia_rx[32, 64 or 128]_port_id[7:0]). the data written to the memory is the spia_rx[32, 64 or 128]_stat and an external status enable (spia_rx[32, 64 or 128]_ext_stat_en) for the selected port. a write is initiated by the fpga by asserting spia_rx[32, 64 or 128]_pss_we high and providing a clock on spia_rx[32, 64 or 128]_pss_clk. the pss block contains a main and shadow calendar table. only one of these calendars is in use at a given time. once a calendar is provisioned with a certain sequence, it is not desirable to change the sequence in that calendar during active device operation. to enable hitless switching of calendars, a shadow calendar is provided. the rx_cal_sel control bit (address 30916 for spia and 30a16 for spib) in the memory map controls the choice. the choice to select a shadow calendar enables hitless bandwidth reprovisioning on the spi4 link. while one cal- endar is being used (e.g. main), the other calendar (shadow) can be con?ured independently with the desired sequence. for more details, refer to the section on calendar programming. the port status sequencer (pss) block polls for port status. it uses the calendar address to decide which port should be polled for status. the status received from the polled port is then formatted into one of the spi4 speci?d status encodings (starving, hungry, satisfied). for every port, the status is polled either from the internal dpram fifo ?gs or the user-provided status bits depending on the external status enable bit. when the external status enable bit for a given port is set to ?? it indicates that the status encoding for that port on the spi4 bus is decided by the external user. when set to ?? the spi4 status encoding is dictated by the status ?gs from the inter- nal dpram banks. the status bits sent to rsp from the pss block is determined according to the truth table shown in table 22. the ?st four columns are the bits of information looked up for the current port id, and the last column is the status that is sent for that selected port to the rsp. table 22. port status encoding k = rx32 or rx64 or rx128 spi4 status logic blocks (rsp, rso) the spi4 receive status protocol (rsp) is responsible for fifo status encoding, calendar management, status pattern encoding (sync bits ?1?, dip-2 calculation and optional calendar selection word encoding (as proposed in appendix g of spi4-02.0 speci?ation). the rsp block performs the following functions: status frame creation virtual fifo virtual fifo spi[a,b]_k_ex t_stat_en spi[a,b]_k_st at[1:0] spi4 status encoding 1 x x x satisfied 0 x 1 ?0 starving 0 x 1 ?1 hungry 0 x 1 ?0 satisfied 0 0 0 x starving 0 1 0 x hungry 0 x 1 ?1 disabled link fill 34 ? fill 12 ? lattice semiconductor orca orspi4 data sheet 84 1036-pin ftsbga devices have been discontinued. decrements calendar_m and calendar_len counters dip-2 calculation the core of the rsp block is the state machine shown in figure 32. the state machine is in the disable state upon reset. setting the register bit rx_status_dis to ? or misalignment on the spi4 rx data interface will cause the state machine to reset to disable state and start sending ?1 on the spi4 status bus. when the received data is aligned and none of the other conditions apply, the state machine transfers to the sync state. the sync state exists for only one clock cycle. in this state the calendar management counters are initialized with the con?ured values from calendar_len_rx and calendar_m_rx. the next state is the cal state if calendar_sw_en bit is set to ? or the switch state if calendar_sw_en bit is set to ?? in the cal state, the counter for calendar_len_rx is decremented on each cycle and the counter for calendar_m_rx is decremented at the end of each calendar sequence. if the calendar_m_rx counter has not reached zero, the calendar_len_rx counter is reset. on each clock cycle, the status is sent out on the rlstat bus. the dip-2 code is calculated in each clock cycle using the method (diagonal xor) described in the oif-spi4-02.0 standard. once both calendar management counters have expired, the calendar management is complete and moves to the dip-2 state. the current dip-2 value coming out of the cal state is xor?d with ?1? the ?al 2-bit dip-2 word is sent out on the rlstat bus and the sync state is entered. if the rx_cal_sw_en bit is enabled (set to ?? then the rsp will insert an extra word into the fifo status frame figure 32. rsp state machine the spi4 receive status output (rso) block contains the low speed lvttl buffers and lvds output buffers nec- essary for the output stage of receive status logic. the option to choose between lvttl or lvds outputs is selected by the software register bit spi4_status_io_sel. calendar programming on a spi4 link, fifo status information is sent periodically over the status link (rstat bus on the spi4 interface) from the device that receives data. the calendar is a means by which the spi4 link conveys information to a data source about the availability of buffer space in the fifos that receive data from that data source. a calendar is a sequence of status messages that provides information on the buffer space for a port or traf? ?w allows user to allocate bandwidth for a port or ?w depending on the overall traf? characteristics. disable sync dip-2 cal switch reset rx_calendar_sw_en = ? rx_calendar_sw_en= ? cal_done rx_cal_len_main/shd, rx_cal_m_main/shd deskewed reset reset reset lattice semiconductor orca orspi4 data sheet 85 1036-pin ftsbga devices have been discontinued. the spi4 status channel operates at 1/8th the spi4 data rate which is reasonable because data is always sent in 16-byte bursts. thus the fastest status update can be expected once in every 8 data clock cycles. for a given port, the frequency with which its status is reported to the far-end transmitter source depends on the allocated band- width for the port. it is imperative that the transmitter and receiver devices are programmed with identical calendar sequences. the following examples illustrate this: suppose a channelized sts-48 has three sts-12 ports and four sts-3 ports (channels), each sts-12 port should have four times the bandwidth of an sts-3 port and 12 times the bandwidth of an sts-1 port within a single calendar cycle. the ?st step is to map each port to an 8-bit port id (address) as shown in table 23 table 23. port id mapping the calendar sequence is as follows: a1, a2, a3, b1, a1, a2, a3, b2, a1, a2, a3, b3, a1, a2, a3, b4 the number of calendar entries is thus 16. this calendar sequence is programmed in the receive calendar memory as follows: this example uses the main calendar. the calendar memory is selected by setting the rx_cal_mem_sel bit (address 30917 in spia and address 30a17 in spib) to ?? writes are done to addresses 0x31000 - 0x3100f. this will correspond to entries 0x00 - 0x0f in the calendar memory. this is shown in table 24. note that the main calendar memory has 1023 locations and can be pro- grammed through addresses 0x31000 - 0x313fe. the shadow calendar memory also has 1023 locations and can be programmed through addresses 0x31400 - 0x317fe. after programming the calendar memory, the rx_cal_mem_set bit is set to ?? the calendar length register rx_cal_len_main is set to 16 (address 30901 and 30902 in spia, 30a01 and 30a02 in spib). rx_cal_m_main (address 30900 in spia and 30a00 in spib) is set to the number of times the calendar sequence needs to be repeated between framing patterns. the shadow calendar can be programmed in the same identical fashion as the main calendar using the steps described above. to enable hitless switching between main and shadow calendar memories, the rx_cal_sw_en bit (address 30916 in spia and 30a16 in spib) should be set to ?? this will cause the receive status logic to insert the calen- dar select word after the framing pattern. the rx_cal_sel bit then selects main (bit set to ?? or shadow (bit set to ?? calendar to be sent on the outgoing status frame. it is important to enable this feature in the transmit device on the other end of the spi4 link by setting tx_cal_sw_en bit (address 30916 in spia and 30a16 in spib) to ?? this will cause the far-end transmit status logic to detect the calendar select word after the framing pattern. port bandwidth 8-bit port id (port address) a1 sts-12 0x00 a2 sts-12 0x01 a3 sts-12 0x02 b1 sts-3 0x03 b2 sts-3 0x04 b3 sts-3 0x05 b4 sts-3 0x06 lattice semiconductor orca orspi4 data sheet 86 1036-pin ftsbga devices have been discontinued. table 24. receive calendar memory contents spi4 receive software interface the spi4 receive interface is con?urable through a system bus interface incorporated within the embedded core. the user can gain access to the system bus either through the integrated mpi interface, or through fpga resources using the system bus master/slave interface. please refer to the appropriate lattice semiconductor data sheets and application notes for more information regarding these interfaces. the receive spi4 interface logic incorporates many con?urable control registers, as well as interrupt and status registers to monitor spi4 performance. table 47 provides a memory map and description of each register within the transmit portion of the spi4 embedded core. timing diagrams as described earlier, there are three main modes of operation - 32-bit mode, 64-bit mode and 128-bit mode. the timing diagrams described below provide a clear picture of each mode of operation. for clarity, all timing diagrams are shown for spia core. they are identical for the spib core. the timing diagram for a 32-bit read access is shown in figure 33. a 3-bit read address spia_rx32_addr_j where j=0,1,2,3 (which is actually the virtual fifo partition address) is sent from the fpga during clock t1. this fifo address should match the virtual fifo address that the user con?ured for a given port in the port descriptor memory (pdm). in other words, the virtual fifo addressed by this 3-bit address contains the data for the port that was mapped to this buffer space in the pdm. the read control logic uses this address to generate the internal physical address. as shown in figure 33, the user sends spia_rx32_rd_j in clock cycle t1. there is a 2-clock latency from the time the read enable spia_rx32_rd_j is asserted to the time read data is presented to the user. thus, in clock cycle t3 following spia_rx32_rd_j, the embedded core provides the 32-bit data and control. the byte enables spia_rx32_be_j[3:0] indicate which bytes within the 32-bit word are valid. if the current port id is different from the previous port id, then the ?st data read from the virtual fifo is the port id as shown in clock cycle t3. the spia_rx32_ctl_j signal is set to ? during t3 indicating that read data contains the port id. the byte enables are set to ?001 indicating that the least signi?ant byte of the 32-bit word contains the port id. if data is continued to be read for the same port, then no port id is presented to the user as this is redundant. the astop_on_eopj is rx calendar memory address rx calendar memory contents (port id) port number 0x00 0x00 a1 0x01 0x01 a2 0x02 0x02 a3 0x03 0x03 b1 0x04 0x00 a1 0x05 0x01 a2 0x06 0x02 a3 0x07 0x04 b2 0x08 0x00 a1 0x09 0x01 a2 0x0a 0x02 a3 0x0b 0x05 b3 0x0c 0x00 a1 0x0d 0x01 a2 0x0e 0x02 a3 0x0f 0x06 b4 lattice semiconductor orca orspi4 data sheet 87 1036-pin ftsbga devices have been discontinued. set to ? which means that the core will terminate a 4-word burst when eop occurs and start transmission of the next set of data. note that a new fifo address ? is provided during the last 4-word burst of address ?? this absorbs the 2-clock latency from the time a new address is presented to the dpram and the time read data is pre- sented to the user. as shown in figure 34, when the astop_on_eopj is asserted, 2 idle clock cycles are inserted after an eop occurs. during these idle cycles, the byte enable bits are set to all ? s indicating that the read data is not valid. after the idle cycles, the core continues to provide read data. the astop_on_eopj signal can be asserted anytime and held high for any length of time during a read data transfer. at any time, the user can poll for the status of a fifo within a dpram bank by providing just the read address spia_rx32_addr_j without providing the read enable. note that the timing diagram shown in figure 33 and fig- ure 34 indicate a fifo size of 16 locations. each location contains four 32-bit data words. thus when spia_rx32_fifo_empty_j ?g is ? and rx_dpram_empty_type_sela[j] software register bit in address 30920 is set to ?? it implies that the fifo has three 4-word data left (1/4 * 16 locations - 1). as shown in figure 35, the err signal indicates that the corresponding packet is in error. the err signal can be asserted by the orspi4 core several clock cycles before eop and remains asserted until eop occurs. however, the user is always required to use the err signal in conjunction with the eop signal. irrespective of the err signal being asserted, the core always transmits the entire packet. thus, it is relevant for the user application to sample the err signal simultaneously with eop. users should also be aware that this is in asymmetry with the transmit spi4 core s behavior. in the transmit direction, user always asserts err signal during an eop only. thus, if any loopback is performed from the receive spi4 (a or b) to the transmit spi4 (a or b), the user should ensure that the received err signal is not wired directly to the corresponding transmit err signal, but follows the transmit protocol of providing an err signal only in the same clock cycle as an eop and not earlier. lattice semiconductor orca orspi4 data sheet 88 1036-pin ftsbga devices have been discontinued. figure 33. read timing with astop_on_eop deasserted - 32-bit mode spia_rx32_ clk_j ?. ?. 123 456 spia_rx32_rd_j n p fifo address changes during last 4-word burst of address n spia_rx32_fifo_ empty_j empty flag is low for fifo address p addressed by n, fifo has three 4-word bursts of data spia_rx32_data_j[31:0] na nb nc nd nc nd pa 2 cycles after read enable port id ?. nb first word of address p spia_rx32_ctl_j spia_rx32_sop_j spia_rx32_eop_j na = word 0 from pointer location in fifo address n nb = word 1 nc = word 2 nd = word 3 pa = word 0 from pointer location in address p fifo size = 16 locations. j = 0 - 3 spia_rx32_addr_j astop_on_eopj 0001 1111 1111 1111 1111 ?. 1111 spia_rx32_be_jj[3:0] 1111 spia_rx32_err_j lattice semiconductor orca orspi4 data sheet 89 1036-pin ftsbga devices have been discontinued. figure 34. read timing with astop_on_eop asserted - 32-bit mode spia_rx32_ clk_j ?. ?. 123 456 spia_rx32_rd_j n spia_rx32_fifo_ empty_j spia_rx32_data_j[31:0] na nb nc nd 2 cycles after read enable port id spia_rx32_ctl_j spia_rx32_sop_j spia_rx32_eop_j na = word 0 from pointer location in fifo address n nb = word 1 nc = word 2 nd = word 3 fifo size = 16 locations. j = 0 - 3 spia_rx32_addr_j astop_on_eopj spia_rx32_be_j[3:0] idle cycles inserted spia_rx32_err_j na nb hf hf h0 h0 hf hf hf hf h1 lattice semiconductor orca orspi4 data sheet 90 1036-pin ftsbga devices have been discontinued. figure 35. read timing with err signal asserted - 32-bit mode in the 64-bit data aggregation mode, dprams 0 and 1 are used as a single memory. similarly, dprams 2 and 3 are combined into a single memory. the timing diagrams for the 64-bit aggregation mode are shown in figure 36, figure 37 and figure 38. as shown in the timing diagrams, read data is always presented to the user in 2 clock cycles of 64-bit data each (plus one additional clock cycle for port id). the exception is during an eop. if eop occurs during the ?st of the two-word data burst, the core terminates the burst and starts to present the next set of data. as shown in figure 36, there is a two-clock cycle latency between the time read enable is asserted by the user and the time data is read from a virtual fifo. in clock cycle t1, the read enable signal spia_rx64_rd_j is asserted along with the virtual fifo (or buffer) address spia_rx64_addr_j. in clock cycle t3, port id is pre- sented followed by two data words in clock cycles t4 and t5. the port id is always present on the least signi?ant byte. this is indicated by the byte enable bits set to ?0000001? as shown in figure 36, fifo address is changed to ? during the last two-word burst from address ?? this is done to absorb the two-clock cycle latency between read address and data. as shown in figure 37, when the astop_on_eopj is asserted, two idle clock cycles are inserted after an eop occurs. during these idle cycles, the byte enable bits are set to all ? s indicating that the read data is not valid. after spia_rx32_ clk_j ?. ?. 123 456 spia_rx32_rd_j n spia_rx32_fifo_ empty_j spia_rx32_data_j[31:0] na nb nc 2 cycles after read enable port id spia_rx32_ctl_j spia_rx32_sop_j spia_rx32_eop_j na = word 0 from pointer location in fifo address n nb = word 1 nc = word 2 nd = word 3 fifo size = 16 locations. j = 0 - 3 spia_rx32_addr_j astop_on_eopj spia_rx32_be_j[3:0] hf hf hf hf h8 hf hf hf h1 spia_rx32_err_j nd na nb nc nd lattice semiconductor orca orspi4 data sheet 91 1036-pin ftsbga devices have been discontinued. the idle cycles, the core continues to provide read data. the astop_on_eopj signal can be asserted anytime and held high for any length of time during a read data transfer. at any time, the user can poll for the status of a fifo within a dpram bank by providing just the read address spia_rx64_addr_j without providing the read enable. note that the timing diagram shown in figure 36, figure 37 and figure 38 indicate a fifo size of 32 locations. each location contains two 64-bit data words. thus when spia_rx64_fifo_empty_j ?g is ? and rx_dpram_empty_type_sela[j] software register bit in address 30920 is set to ?? it implies that the fifo has 7 two-word data left (1/4 * 32 locations - 1). as shown in figure 38, the err signal indicates that the corresponding packet is in error. the err signal can be asserted by the orspi4 core several clock cycles before eop and remains asserted until the clock cycle when eop is asserted. however, the user is always required to use the err signal in conjunction with the eop signal. irrespective of the err signal being asserted, the core always transmits the entire packet. thus, it is relevant for the user application to sample the err signal simultaneously with eop. users should also be aware that this is in asymmetry with the transmit spi4 core s behavior. in the transmit direction, user always asserts err signal during an eop only. thus, if any loopback is performed from the receive spi4 (a or b) to the transmit spi4 (a or b), the user should ensure that the received err signal is not wired directly to the corresponding transmit err signal, but follows the transmit protocol of providing an err signal only in the same clock cycle as an eop and not earlier. figure 36. read timing with astop_on_eop deasserted - 64-bit mode ?. ?. 123 4 56 fifo size = 32 spia_rx64_clk_j spia_rx64_rd_j spia_rx64_addr_j n address changed to partition/fifo p during last 2-word burst in address n p spia_rx64_fifo_empty_j indicates fifo has seven 2-word bursts fifo empty low for address p port id spia_rx64_data_j[63:0] na nb ?. na nb port id pa spia_rx64_ctl_j spia_rx64_sop_j spia_rx64_eop_j j=0,1 astop_on_eopj h01 hff hff ?. hff hff h01 spia_rx64_be_j[7:0] spia_rx64_err_j lattice semiconductor orca orspi4 data sheet 92 1036-pin ftsbga devices have been discontinued. figure 37. read timing with astop_on_eop asserted - 64-bit mode spia_rx64_clk_j ?. ?. 123 456 spia_rx64_rd_j n spia_rx64_fifo_empty_j spia_rx64_data_j[63:0] na nb na 2 cycles after read enable port id spia_rx64_ctl_j spia_rx64_sop_j spia_rx64_eop_j na = word 0 from pointer location in fifo address n nb = word 1 fifo size = 32 locations. spia_rx64_addr_j astop_on_eopj spia_rx64_be_j[7:0] idle cycles inserted j = 0,1 spia_rx64_err_j nb na nb h00 h00 hff hff hff hff hff h01 hff lattice semiconductor orca orspi4 data sheet 93 1036-pin ftsbga devices have been discontinued. figure 38. read timing with err asserted - 64-bit mode in the 128-bit data aggregation mode, dprams 0,1,2 and 3 are used as a single contiguous memory. all dprams must be con?ured identically by software. in 128-bit aggregation mode, a maximum of 8 per-port buffers are pos- sible. one signi?ant difference between the 128-bit mode and the 32-bit and 64-bit modes is that the port id is presented to the user on a separate bus (spia_rx128_portid[7:0]). thus the spia_rx128_ctl signal has no relevance to the user and can be ignored. read data is presented as a 128-bit word every clock cycle. as shown in figure 39, read enable spia_rx128_rd and address spia_rx128_addr are presented in clock cycle t1. in t3 read data is available to the user after 2 clock cycles of latency. the fifo address is changed to ? during the sec- ond last word of address ? such that the 2 clock cycles of latency between address and data can be absorbed. as shown in figure 40, when the astop_on_eop is asserted, two idle clock cycles are inserted after an eop occurs. during these idle cycles, the byte enable bits are set to all ?s indicating that the read data is not valid. after the idle cycles, the core continues to provide read data. the astop_on_eop signal can be asserted anytime and held high for any length of time during a read data transfer. at any time, the user can poll for the status of a fifo within a dpram bank by providing just the read address spia_rx128_addr without providing the read enable. note that the timing diagram shown in figure 39, figure 40 and figure 41 indicate a fifo size of 64 locations. each location contains a 128-bit word. thus when spia_rx64_clk_j ?. ?. 123 456 spia_rx64_rd_j n spia_rx64_fifo_empty_j spia_rx64_data_j[63:0] 2 cycles after read enable spia_rx64_ctl_j spia_rx64_sop_j spia_rx64_eop_j na = word 0 from pointer location in fifo address n nb = word 1 fifo size = 32 locations. spia_rx64_addr_j astop_on_eopj spia_rx64_be_j[7:0] j = 0,1 spia_rx64_err_j hff hff hff hff hff hff hff hff h01 na nb na nb port id na nb na nb lattice semiconductor orca orspi4 data sheet 94 1036-pin ftsbga devices have been discontinued. spia_rx128_fifo_empty ?g is ? and rx_dpram_empty_type_sela[0:3] software register bits in address 30920 are set to ?? it implies that the fifo has 15 128-bit words left (1/4 * 64 locations - 1). as shown in figure 41, the err signal indicates that the corresponding packet is in error. the err signal can be asserted by the orspi4 core several clock cycles before eop and remains asserted until the clock cycle when eop is asserted. however, the user is always required to use the err signal in conjunction with the eop signal. irrespective of the err signal being asserted, the core always transmits the entire packet. thus, it is relevant for the user application to sample the err signal simultaneously with eop. users should also be aware that this is in asymmetry with the transmit spi4 core s behavior. in the transmit direction, user always asserts err signal during an eop only. thus, if any loopback is performed from the receive spi4 (a or b) to the transmit spi4 (a or b), the user should ensure that the received err signal is not wired directly to the corresponding transmit err signal, but follows the transmit protocol of providing an err signal only in the same clock cycle as an eop and not earlier. figure 39. read timing with astop_on_eop deasserted - 128-bit aggregation mode ?. 123 456 fifo size = 64 spia_rx128_clk spia_rx128_rd spia_rx128_addr n p address changed when penultimate word is read from fifo n spia_rx128_empty fifo empty for address p indicates fifo has 15 words left spia_rx128_data ?. data read 2 cycles after address changed to p 2 cycles after read enable spia_rx128_portid port id port id spia_rx128_sop spia_rx128_eop hffff ?. hffff hffff hffff spia_rx128_be spia_rx128_err astop_on_eop d0 d1 d63 d62 d2 p0 lattice semiconductor orca orspi4 data sheet 95 1036-pin ftsbga devices have been discontinued. figure 40. read timing with astop_on_eop asserted - 128-bit mode spia_rx128_clk ?. ?. 123 456 spia_rx128_rd n spia_rx128_fifo_empty spia_rx128_data d1 d2 d3 d4 2 cycles after read enable d0 spia_rx128_sop spia_rx128_eop fifo size = 64 locations. spia_rx128_addr astop_on_eop d0 d1 spia_rx128_be hffff hffff hffff hffff h0000 h0000 hffff hffff idle cycles inserted hffff spia_rx128_err lattice semiconductor orca orspi4 data sheet 96 1036-pin ftsbga devices have been discontinued. figure 41. read timing with err asserted - 128-bit mode special operating modes static capture mode the orspi4 receiver supports both dynamic and static capture of data at the high-speed spi4 interface. all the operating modes (32-bit, 64-bit and 128-bit) are independent of the type of data capture. they can operate in either static or dynamic capture mode. the choice of static vs. dynamic alignment depends on the spi4 data rates. the static data capture is valid in the frequency range 400-700 mbps. it also reduces the power dissipation of the device. the following control signals are relevant to enable static data capture: spi4_low_speed_data_sel : this is a software register control bit (address 30915 in spia and 30a15 in spib). when set to ?? the dynamic alignment circuit is held in a reset state and the static alignment mode is enabled. spi_datm_a or spi_datm_b : this is a control signal from the fpga. when set to ?? this gives the user the option to skew the rdclk with respect to the spi4 data bus rdat on the bus by choosing delay taps through the control bits spi_dlytap_a[2:0] of spi_dlytap_b[2:0]. when set to ?? rdclk is automatically centered on-chip to the input data bus rdat. quarter-rate mode spia_rx128_clk ?. ?. 123 456 spia_rx128_rd n spia_rx128_fifo_empty spia_rx128_data d1 d2 d3 d4 2 cycles after read enable d0 spia_rx128_sop spia_rx128_eop fifo size = 64 locations. spia_rx128_addr astop_on_eop d0 d1 spia_rx128_be spia_rx128_err d2 d3 hffff hffff hffff hffff hffff hffff hffff hffff hffff lattice semiconductor orca orspi4 data sheet 97 1036-pin ftsbga devices have been discontinued. the orspi4 spi4 rx interface is also designed to operate at data rates much lower than 622 mbps. even though the oif standard speci?s a minimum data rate of 622 mbits/s, the lower data rates are provided for users who wish to use the spi4 link for applications supporting <10 gbits/s aggregate bandwidth (sts-48, sts-3, gb ether- net, etc.). to enable this low speed mode, user should set the software register bit spi4_quarter_rate (address 30915 in spia and 30a15 in spib) to ?? this supports data rates in the range of 100 - 200 mbps. this bit takes precedence over spi4_low_speed_data_sel, since setting this bit to ? will automatically reset the dynamic alignment block irrespective of spi4_low_speed_data_sel register bit setting. spi4 loopback modes there are three forms of loopback supported directly by the orspi4 spi4 blocks. high-speed near end loopback: this involves looping back data from the high-speed transmit block tdo serial output to the high-speed receive block rdi serial input (see fig. 42). all of the logic excluding the lvds buffers is included in the loopback path. the status path is looped from the output of the rsp block to the tsp block. this mode is enabled by setting the control register bit spi4_loopbk_hs to 1. far end loopback: this involves looping back the 128-bit output data from the rdi block to the 128-bit input of the tdo block (see fig. 43). data is received at the high-speed spi4 rx interface and transmitted at the spi4 tx interface. the status path is looped from tstat to rs tat. this mode is enabled by setting control register bit spi4_loopbk_fe to ?? low-speed near end loopback which excludes the high-speed blocks from the loopback path: this involves sourcing data from the fpga, looping back the output of tdp block into rdp block and observing data at the core-fpga boundary (see fig. 44). the status path is looped from the rsp block to the tsp block. this form of loopback will require an additional low-speed clock source (tstclk) and is enabled by setting control register bit spi4_loopbk_ls to ? and enabling spi4_loopbk_hs. figure 42. high-speed near end loopback tdat[15:0] tctl tdclk spi4 i/f tdo trefclk tstat[1:0] tsclk rdat[15:0] rctl rdclk rdi rstat[1:0] rsclk tdp 128-bit data+ctl tsp clk dprams + associated logic port write sequencer tx fpga rdp rsp dprams + associated logic port status sequencer clk 128-bit data+ctl clk rx embedded core lattice semiconductor orca orspi4 data sheet 98 1036-pin ftsbga devices have been discontinued. figure 43. far end loopback far end loopback setup the following three step procedure will set up the orspi4 into far end loopback mode: 1. set up the external connections to the orspi4 such that the rdat, rdclk, and rctl spi-4 ports are all receiving signals. (if in quarter rate mode, the fpga-sourced clock reference signal spi[a,b]_trefclk_x8 must be supplied at twice the rate as the applied [a,b]rdclk spi-4 port clock. 2. con?ure the appropriate orspi4 register as shown in table 25. note that either choice of lvttl or lvds for status buffer is acceptable for far end loopback, although the choice will affect the status port timing. also note that bits 6 and 7 (tx_force_dip4_err and rx_force_dip2_err) do not affect the operation of far end loopback. 3. reset the appropriate spi4 block with control signal fpga_reset_s4[a,b]. tdat[15:0] tctl tdclk spi4 i/f tdo trefclk tsi tstat[1:0] tsclk rdat[15:0] rctl rdclk rdi rso rstat[1:0] rsclk tdp 128-bit data+ctl tsp dprams + associated logic port write sequencer tx fpga rdp rsp dprams + associated logic port status sequencer clk 128-bit data+ctl clk rx embedded core lattice semiconductor orca orspi4 data sheet 99 1036-pin ftsbga devices have been discontinued. table 25. far end loopback register values absolute address (hex) bit name description quarter rate far end static far end dynamic far end 30915 (spi a) 30a15 (spi b) [0] spi4_quarter_rate when set to ?? enables data rates of 100 - 200 mbps. the plls in the transmit and receive spi4 high-speed blocks are bypassed in this mode. 100 [1] spi4_loopbk_fe this control enables far-end loopback when it is set to 1. far end loopback sends rdat inputs back to tdat outputs, sends rdclk back to tdclk, sends tstat back to rstat outputs, and atsclk back to rsclk. 111 [2] spi4_low_speed_ data_sel forces low speed data rates of 400-622 mbits/s. the transmit pll is still used to synthesize the spi4 transmit clock tdclk. however, the dynamic alignment block in the receive side is bypassed. no training sequences are used in low speed mode. 110 [3] spi4_status_io_sel ? - selects lvttl i/o for spi4 status. ? - selects lvds i/os for spi4 status (full-rate lvds status i/os speci?d by oif spi4.0 is not supported). 0 or 1 0 or 1 0 or 1 [4] spi4_loopbk_hs enables loops from high-speed spi4 tdat out- puts to rdat inputs and rstat to tstat status inputs just before i/o. 000 [5] spi4_loopbk_ls enables near-end parallel loopback from tdp to rdp blocks and rsp to tsp blocks bypassing the high-speed spi4 interface logic blocks. must enable spi4_loopbk_hs for this to work. 000 [6] tx_force_dip4_err x x x [7] rx_force_dip2_err x x x lattice semiconductor orca orspi4 data sheet 100 1036-pin ftsbga devices have been discontinued. figure 44. low-speed near end loopback (excluding high-speed blocks) spi4 error insertion capabilities the spi4 blocks support the following error insertion options for testing: dip-4 odd parity is calculated over data and control words on the tx side. under software control, dip-4 errors can be forced by inverting the dip-4 parity bits. this is done by setting tx_force_dip4_err bit to ? (address 30915 in spia and 30a15 in spib). dip-2 odd parity is calculated over the status frames on the rx side. under software control, dip-2 errors can be forced by inverting the dip-2 parity bits. this feature can be enabled by setting rx_force_dip2_err to ? (address 30915 in spia and 30a15 in spib). spi4 status reporting capabilities the following status information will be reported through status registers. most status registers also cause inter- rupts. the interrupts can be masked by the corresponding interrupt enables. dip-4, dip-2 errors (these cause interrupts). the associated register status bits are: rx_algn_off_sts, tx_status_lof_sts, rx_dip4_err_sts, tx_dip2_err_sts dip-4, dip-2 error counters. these are 8-bit counters. the status registers are: rx_dip4_err_cnt, tx_dip2_err_cnt deskew status and error from high-speed rx side. these cause an interrupt. the associated register status bits are: rx_dskw_done_sts, rx_dskw_err_sts dpram fifo overruns and underruns (rx and tx dpram memories). these can cause an interrupt. spia or spib receive pll loss of lock indicator. the associated register bit is ?x_pll_lol_sts tdat[15:0] tctl tdclk spi4 i/f tdo trefclk tstat[1:0] tsclk rdat[15:0] rctl rdclk rdi rstat[1:0] rsclk tdp 128-bit data+ctl b tsp clk dprams + associated logic port write sequencer tx fpga rdp rsp dprams + associated logic port status sequencer clk 128-bit data+ctl clk rx embedded core lattice semiconductor orca orspi4 data sheet 101 1036-pin ftsbga devices have been discontinued. orspi4 spi4 clocking transmit clocking the following descriptions and ?ures show the spia core. the spib core is identical. figure 45. spi4 tx clocking atrefclk: external pad. reference clock for the high-speed spia transmit block. its frequency is 1/4th the spi4 line clock atdclk. the atrefclk pad should be tied off during quarter-rate mode. spia_trefclk_x8: reference clock source from the fpga when spia is operating in quarter-rate mode. its fre- quency is two times the spi4 line clock. i.e. if spi4 line clock is 100 mhz, this clock is 200 mhz. maximum allow- able frequency is 200 mhz. atdclk[p,n]: external output pads. spi4 transmit data clock. spi4 transmit data atdat and atctl are valid on both edges of this clock. atsclk[p,n] : external input lvds pads. spi4 transmit status clock. tsclka: external input 3.3v lvttl transmit status input. spia_txk_clk_j: write clocks from fpga to each of the four asynchronous dprams. (j = 0, 1, 2 or 3) (k = 32, 64 or 128) atrefclk_f: clock output to the fpga. its frequency is the same as atrefclk. it is used to clock the status outputs to the fpga, namely spia_txk_port_id, spia_txk_stat and spia_txk_burst_val. spia tx status spia tx core (data) fpga spia_txk_clk_0 spia_txk_clk_1 spia_txk_clk_2 spia_txk_clk_3 spia_trefclk_x8 atrefclk_f k= 32, 64, or 128 atrefclk atdclkp atdclkn atsclkp atsclkn tsclka lvttl input lvds input lattice semiconductor orca orspi4 data sheet 102 1036-pin ftsbga devices have been discontinued. receive clocking the following descriptions and ?ures show the spia core. the spib core is identical. figure 46. spi4 rx clocking ardclk[p,n]: spi4 line clocks received with data and control. these are external lvds input pads. spia_rxk_clk_j: read clocks to each of the four asynchronous dprams. arlsclk_f: output clock from receive status logic to fpga. spia_rxk_pss_clk: write clocks from fpga to the receive status ram. the arlsclk_f clock can be used to source this clock as shown by dotted lines in the ?ure. arsclk[p,n]: lvds receive status outputs. external pads. rsclka: 3.3 v lvttl receive status output. external pads. spia rx status spia rx core (data) fpga spia_rxk_clk_0 spia_rxk_clk_1 spia_rxk_clk_2 spia_rxk_clk_3 arlsclk_f k = 32, 64, or 128 ardclkp ardclkn arsclkp arsclkn rsclka lvttl input lvds output j =0, 1, 2 or 3 spia_rxk_pss_clk lattice semiconductor orca orspi4 data sheet 103 1036-pin ftsbga devices have been discontinued. serdes functional description the serdes portion of the orspi4 contains four clock and data recovery (cdr) macrocells and serial- ize/deserialize (serdes) blocks and supports 8b/10b (ieee 802.3.2002) encoded serial links. it is intended for high-speed serial backplane data transmission. figure 47 shows the serdes top level block diagram and the basic data ?w to and from the serdes. boundary scan for the serdes only includes programmable i/os and does not include any of the embedded block i/os. figure 47. serdes top level block diagram. the serdes serial channels can each operate at up to 3.7 gbits/s (2.96 gbits/s data rate) with a full-duplex syn- chronous interface with built-in clock recovery (cdr). the 8b/10b encoding provides guaranteed ones density for the cdr, byte alignment, and error detection. the core is also capable of frame synchronization and physical link monitoring. overviews of the various blocks in the serdes are presented in the following paragraphs orspi4 serdes functional block overview the serdes portion of the core contains one transceiver block for serial data transmission at a selectable data rate of 0.6-3.7 gbits/s. each serdes channel features high-speed 8b/10b parallel i/o interfaces to other core blocks and high-speed cml interfaces to the serial links. the serdes circuitry consists of receiver, transmitter, and auxiliary functional blocks. the receiver accepts high- speed (up to 3.7 gbits/s) serial data. based on data transitions, the receiver locks an analog receive pll for each channel to retime the data, then de-multiplexes the data down to parallel bytes and an accompanying clock. the transmitter operates in the reverse direction. parallel bytes are multiplexed up to 3.7 gbits/s serial data for off- chip communication. the transmitter generates the necessary high-speed clocks for operation from a lower speed reference clock. the transceivers are controlled and con?ured through the system bus in the fpga logic and through the external 8-bit microprocessor interface of the fpga. each channel has associated dedicated registers that are readable and write-able. there are also global registers for control of common circuitry and functions. the serdes performs 8b/10b encoding and decoding for each channel. the 8b/10b transmission code can sup- port either ethernet or fibre channel speci?ations for serial encoding/decoding, special characters, and error detection. the user can disable the 8b/10b decoder to receive raw 10-bit words which will be rate reduced by the serdes. if this mode is chosen, the user must bypass the multi-channel alignment fifos. serdes w/ clock/data byte- wide data 8b/10b decoder/encoder 4 full- 0.6 gbits/s data duplex serial channels to 3.7 gbits/s 0.6 gbits/s data to 3.7 gbits/s cml i/os orca series 4 fpga logic standard fpga i/os 4:1 mux/1:4 demux recovery lattice semiconductor orca orspi4 data sheet 104 1036-pin ftsbga devices have been discontinued. the serdes block contains its own dedicated plls for both transmit and receive clock generation. the user pro- vides a reference clock of the appropriate frequency. the receiver plls extract the clock from the serial input data and retime the data with the recovered clock. mux/demux block the mux/demux block converts the data format for the high-speed serial links to a wide, low-speed format for crossing the core/fpga interface. the intermediate interface to the serdes macrocell runs at 1/10th the bit rate of the data lane. the mux/demux converts the data rate and bus width so the interface to the fpga core can run at 1/4th this intermediate frequency, giving a range of 25.0-92.5 mhz for the data rates into and out of the fpga logic. multi-channel alignment fifos the four incoming data channels can be independent of each other, or can be synchronized in several ways. two channels within a serdes block can be aligned together; channels a and b and/or channels c and d. alterna- tively, four channels in a serdes block can be aligned together to form a communication channel with a band- width of 10 gbits/s. individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other chan- nels. xaui and fibre channel link state machines two separate link state machines are included in the architecture. a xaui link state machine is included in the serdes, modeled after the ieee 802.3ae standard. a separate state machine for fibre channel is also imple- mented. fpga/serdes interface in 8b/10b mode, the fpga logic will receive/transmit 32-bits of data (up to 92.5 mhz) and four k_ctrl bits from/to the serdes. there are eight data streams in each direction plus additional timing, status and control signals. data sent to the fpga can be aligned using comma (/k/) characters or the /a/ character as speci?d either by fibre channel or by ieee 802.3ae for xaui based interfaces. the alignment character is made available to the fpga along with the data. the special characters k28.1, k28.5 and k28.7 are treated as valid comma characters by the serdes. if the receive channel alignment fifos are bypassed, then each channel will provide its own receive clock in addi- tion to data and comma character detect signals. if the 8b/10b decoders are bypassed, then 40-bit data streams are passed to the fpga logic. no channel alignment can be done in 8b/10b bypass mode. the following table summarizes the interface signals between the fpga logic and the core. in the table, an input refers to a signal ?wing into the serdes and an output refers to a signal ?wing out of the serdes. table 26. fpga/serdes interface description fpga/embedded core inter- face signal name (x = [a, ..,d]) input (i) to or output (o) from core signal description transmit path signals twdx[31:0] fpga core transmit data?hannel x. tcommax[3:0] fpga core transmit comma character?hannel x. tbit9x[3:0] fpga core transmit force negative disparity?hannel x tsys_clk_x fpga core transmit low-speed clock to the fpga?hannel x tck78 core fpga transmit low-speed clock to the fpga?erdes quad receive path signals mrwdx[39:0] core fpga receive data?hannel x (see table 35). rwckx core fpga low-speed receive clock?hannel x. lattice semiconductor orca orspi4 data sheet 105 1036-pin ftsbga devices have been discontinued. backplane transceiver core detailed description the following sections describe the various logic blocks in the serdes portion of the fpsc. for a detailed description of the programmable logic functions, please see the orca series 4 fpga data sheet and related application and technical notes. the major functional blocks in the serdes include: one serializer-deserializer (serdes) block and clock and data recovery (cdr) circuitry 8b/10b encoder/decoders transmit pre-emphasis circuitry 4-to-1 multiplexers (mux) and 1-to-4 demultiplexers (demux) fibre channel synchronization state machine xaui link alignment state machine alignment fifos a top level block diagram of the serdes logic is shown in figure 48. figure 48. top level block diagram, serdes embedded core logic rck78 core fpga receive low-speed clock to fpga?erdes quad. rsys_clk_1 fpga core low-speed receive fifo clock for channels a, b rsys_clk_2 fpga core low-speed receive fifo clock for channels c, d cv_selx fpga core enable detection of code violations in the incoming data sys_rst_n fpga core synchronous reset of the channel alignment blocks. fpga_reset_fc fpga core disables access to serdes when high logic common to quad channel b channel d backplane serial links receive channel a 2:1 mux (x40) demux block link state machine rx ser- des block multi - channel alignment block tx serdes block interface and mux block transmit channel a rck78 tck78 mrwda[39:0] cv_sela rwcka tsys_clk_a twda[31:0] tcomma[3:0] . . . fpga logic . . . hdout[p:n]_a hdin[p:n]_a refclk[p:n] 2 channel c 2 2 lattice semiconductor orca orspi4 data sheet 106 1036-pin ftsbga devices have been discontinued. serdes detailed description the serdes provides transceiver functionality for four serial data channels. each channel is identi?d by a chan- nel identi?r [a:d]. the data channels can operate independently or they can be combined together (aligned) to achieve higher bit rates. the mode operation of the core is de?ed by a set of control registers, which can be written through the sys- tem bus interface. also, the status of the core is stored in a set of status registers, which can be read through the system bus interface. the transmitter section for each channel accepts 40 bits (raw mode) of data or 32-bits of data and eight con- trol/status bits from the fpga logic and (optionally) encodes the data using 8b/10b encoding. it also accepts the low-speed reference clock at the refclk input and uses this clock to synthesize the internal high-speed serial bit clock. the data is then serialized and the serialized data are available at the differential cml output terminated in 86 to drive either an optical transmitter or coaxial media or circuit board/backplane. the receiver section receives high-speed serial data at its differential cml input port. these data are fed to the clock recovery section, which generates a recovered clock and retimes the data. the retimed data are also de-seri- alized and optionally 8b/10b decoded. the receiver also (optionally) recognizes the comma characters or code vio- lations and aligns the bit stream to the proper word boundary. the resulting parallel data is (optionally) passed to the multi-channel alignment block before it is presented to the fpga logic. 8b/10b encoding and decoding in 8b/10b mode, the fpga logic will receive/transmit 32-bits of data and four k_ctrl bits from/to the embedded core. in the transmit direction, four additional input bits can force a negative disparity present state. the serdes logic will encode the data to, or decode the data from, a 10-bit format according to the fc-ph ansi x3.230:1994 standard (which is also the encoding used by the ieee 802.3ae ethernet standard). this encoding/decoding scheme also allows for the transmission of special characters and supports error detection. following the de?itions and conventions used in de?ing the 8b/10b coding rules, each valid coded character has a name corresponding to its 8-bit binary value: dx.y for data characters kx.y for special characters x = the 5-bit input value, base 10, for bits abcde y = the 3-bit input value, base 10, for bits fgh an 8b/10b encoder is designed to maintain a neutral average disparity. disparity is the difference between the number of ?? and ?? in the encoded word. neutral disparity indicates the number of ?? and ?? are equal. positive disparity indicates more ?? than ??. negative disparity indicates more ?? than ??. the average dis- parity determines the dc component of the signals on the serial line. running disparity is a record of the cumula- tive disparity of every encoded word, and is tracked by the encoder. in order to maintain neutral disparity, two different codings are de?ed for each data value. the 8b/10b encoder in the transmit path selects between (+) and (-) encoded word based on calculated disparity of the present data to maintain neutral disparity. in the receive path, the clock and data recovery blocks retime the incoming data and 8b/10b decoders generate 8- bit data based on the received 10-bit data. a sequence of valid 8b/10b coded characters has a maximum run length of 5-bits (i.e., ?e consecutive ?? or ?e consecutive ?? before a mandatory bit transition). this assures adequate transitions for robust clock recovery. the recovered data is aligned on a 10-bit boundary by detecting and aligning to special characters in the incoming data stream. data is word-aligned using the comma (/k/) character. a comma character is a special character that contains a unique pattern (0011111 or its complement 1100000) in the 10-bit space that makes it useful for delim- lattice semiconductor orca orspi4 data sheet 107 1036-pin ftsbga devices have been discontinued. iting word boundaries. the special characters k28.1, k28.5 and k28.7 contain this comma sequence and are treated as valid comma characters by the serdes. the following table shows all of the valid special characters. all of the special characters are made available to the fpga logic; however only the comma characters are used by the serdes logic. the different codings that are possible for each data value are shown as encoded word (+) and encoded word (-). the table also illustrates the 8b/10b bit labeling convention. the bit positions of the 8-bit characters are labeled as h,g,f,e,d,c,b and a and the bit positions of the 10-bit encoded characters are labeled as a, b, c, d, e, i, f, g, h, and j. the encoded words are transmitted serially with bit 'a' transmitted ?st and bit 'j' transmitted last. transmit path (fpga to backplane) logic the transmitter section accepts four groups of either 8-bit unencoded data or 10-bit encoded data at the parallel interface to the fpga logic. it also uses the reference clock, refclk[p:n] to synthesize an internal high-speed serial bit clock. the serialized transmitted data are available at the differential cml output pins to drive either an optical transmitter, coaxial media or a circuit board backplane. as shown in figure 49, the basic blocks in the transmit path include: serdes/fpga interface and 4:1 multiplexer low speed parallel core/fpga interface 4:1 multiplexer transmit serdes 8b/10b encoder 10:1 multiplexer cml output buffer detailed descriptions of the logic blocks are given in following sections. detailed descriptions of transmit clock dis- tribution, including the transmit pll are given in later sections of this data sheet. table 27. valid special characters k character hgf edcba 765 43210 k control encoded word (? encoded word (+) abcdei fghj abcdei fghj k28.0 000 11100 1 001111 0100 110000 1011 k28.1 /comma/ 001 11100 1 001111 1001 110000 0110 k28.2 010 11100 1 001111 0101 110000 1010 k28.3 /a/ 011 11100 1 001111 0011 110000 1100 k28.4 100 11100 1 001111 0010 110000 1101 k28.5 /comma/ 101 11100 1 001111 1010 110000 0101 k28.6 110 11100 1 001111 0110 110000 1001 k28.7 /comma/ 111 11100 1 001111 1000 110000 0111 k23.7 111 10111 1 111010 1000 000101 0111 k27.7 111 11011 1 110110 1000 001001 0111 k29.7 111 11101 1 101110 1000 010001 0111 k30.7 111 11110 1 011110 1000 100001 0111 lattice semiconductor orca orspi4 data sheet 108 1036-pin ftsbga devices have been discontinued. figure 49. basic logic blocks, transmit path, single channel (typical reference clock frequency) serdes/fpga logic interface and 4:1 multiplexer these blocks provide the data formatting and transmit data and clock signal transfers between the serdes and the fpga logic. control and status registers in the fpga portion of the chip control the transmit logic and record status. these bits are passed to the core using the fpga system bus and are described in later sections of this data sheet. the low-speed transmit interface consists of a clock and 4 data bytes, each with an accompanying control bit. the data bytes are conveyed to the mux via the twdx[31:0] ports (where x represents the channel label [a,b,c or d]. the control bits are tcommax[3:0] which de?e whether the input byte is to be interpreted as data or as a special character and tbit9x[3:0] which are used to force a negative disparity present state. the data and control signals are synchronized to the transmit clock, tsys_clk_x. both the data and control are strobed into the core on the rising edge of tsys_clk_x. note that each tbit9x[3:0] controls the disparity of the encoded version of its corre- sponding data byte. setting bit tbit9c[3] to ?? for instance, will force the 8b/10b encoder to asserts a current neg- ative running disparity state. this will cause it to encode twdc[31:24] positively (more ??s than ??s). setting tbit9x to 0 will leave the encoder free to alternate between positive and negative encoding to maintain a zero run- ning disparity. the mux is responsible for taking 40 bits of data/control at the low-speed transmit interface and up-converting it to 10 bits of data/control at the serdes transmit interface. the mux has two clock domains - one based on the clock received from the serdes block and a second that comes from the fpga at 1/4 the frequency of the serdes clock. the time sequence of interleaving data/control values is shown in figure 50. 4 fifo 4:1 mux (x9) pll prbs gen. cml buffer with pre- emphasis 10:1 mux 8b/10b encoder (with bypass) interface and mux block tx serdes block stbd_x[7:0] stbd_x[8] stbd_x[9] stbc311_x 8 8-bit data k-control force-ve disparity 312.5 mhz hdoutp_x hdoutn_x refclkp refclkn cml buffer backplane serial link fpga logic twdx[31:0] 32 tcommax[3:0] 4 tbit9x[3:0] 4 tsys_clk_x mux tck78 78.125 mhz tcksel[0:1] logic common to quad from other 3 channels to other 3 channels from control register { { note: x= [a, b, ... d] 156.25 mhz lattice semiconductor orca orspi4 data sheet 109 1036-pin ftsbga devices have been discontinued. figure 50. transmit mux block timing - single channel . (note: xx = a, b, c, or d) serdes block the serdes block accepts either 8-bit data to be encoded or 10-bit unencoded data at the parallel input port from the mux/demux block. it also accepts the reference clock at the refclk input and uses this clock to synthesize the internal high-speed serial bit clock. the internal stbc311x clock is derived from the reference clock. the frequency of this clock depends on the set- ting of the half-rate/full-rate control bit setting the mode of the serdes and the frequency of the refclk and/or that of the high-speed serial data. a falling edge on the stbc311x clock port will cause a new data character to be transferred into the serdes block. the latency from the serdes block input to the high-speed serial output is ?e stbc311x clock cycles, as shown in figure 51. figure 51. transmit path timing - single serdes channel (note: xx = a, b, c, or d) each block also sends a clock to the fpga logic. this clock, tck78[a,b], is sourced from one of the four mux blocks and has the same frequency as tsys_clk_x, but arbitrary phase. within each mux block, the low fre- quency clock output is obtained by dividing by four, the serdes stbc311x clock, which is used internally to syn- chronize the transmit data words. tcksel control bits select the channel to source tck78. the internal signals stbdx[9:0] (where x is represents a, b, c or d) from the mux block carry unencoded character data and control bits. the 10th bit (stbdx[9]) of each data lane into the serdes is used to force a negative disparity present state. pqrs t xyz stbdxx[9:0] latency = 4 tsys_clk_xx clocks twdxx[31:24], tsys_clk_xx 10-bit wide data twdxx[23:16], twdxx[15:8], tcommaxx[3] tcommaxx[2] tcommaxx[1] tcommaxx[0] twdxx[7:0], tbit9xx[0] tbit9xx[1] tbit9xx[2] tbit9xx[3] p 7-0 p 8 p 9 t 7-0 t 8 t 9 q 7-0 q 8 q 9 x 7-0 x 8 x 9 r 7-0 r 8 r 9 y 7-0 y 8 y 9 s 7-0 s 8 s 9 z 7-0 z 8 z 9 pq r s t xyz stbdxx[9:0] stbc311xx hdout_xx p 4 p 5 p 6 p 7 p 8 p 9 p 0 p 1 p 2 p 3 latency = 5 stbc311x clocks lattice semiconductor orca orspi4 data sheet 110 1036-pin ftsbga devices have been discontinued. 8b/10b encoder and 1:10 multiplexer the 8b/10b encoder encodes the incoming 8-bit data into a 10-bit format as described previously. the input signals to the block, stbdx[7:0] are used for the 8-bit unencoded data. stbdx[8] is used as the k_control input to indicate whether the 8 data bits need to be encoded as special characters (k_control = ?? or as data characters (k_control = 0). when stbdx[9:0] = ?? a negative disparity present state is forced. when the encoder is bypassed stbdx[9:0] serve as the data bits for the 10-bit unencoded data. within the 8b/10b transmission code, the bit positions of the 10-bit encoded transmission characters are labeled as a, b, c, d, e, i, f, g, h, and j in that order. bit a corresponds to stbdx[0], bit b to stbdx[1], bit c to stbdx[2], bit d to stbdx[3], bit e to stbdx[4], bit i to stbdx[5], bit f to stbdx[6], bit g to stbdx[7], bit h to stbdx[8], and bit j to stbdx[9]. the 10-bit wide parallel data is converted to serial data by the 10:1 multiplexer. the serial data are then sent to the cml output buffer and are transmitted serially with stbdx[0] transmitted ?st and stbdx[9] transmitted last. cml output buffer the transmitter's cml output buffer is terminated on-chip in 86 ohms to optimize the data eye, as well as to reduce the number of discrete components required. the differential output swing reaches a maximum of 1.2 v pp in the normal amplitude mode. a half amplitude mode can be selected via con?uration register bit hamp_x. half ampli- tude mode can be used to reduce power dissipation when the transmission medium has minimal attenuation or for testing of the integrity (loss) of the physical medium. a programmable preemphasis circuit is provided to boost the high frequencies in the transmit data signal to maxi- mize the data eye opening at the far-end receiver. preemphasis is particularly useful when the data are transmitted over backplanes or low-quality coax cables which have a frequency-dependent amplitude loss. for example, for fr4 material at 2.5 ghz, the attenuation compared to the 1.0 ghz value is about 3 db. the attenuation is a result of skin effect loss of the pcb conductor and the dielectric loss of the pcb substrate. this attenuation causes intersymbol interface which results in the closing of the data eye opening at the receiver. since this effect is predict- able for a given type of pcb material, it is possible to compensate for this effect in two ways - transmitter preem- phasis and receiver equalization. each of these techniques boosts the high frequency components of the signal but transmit preemphasis is preferred due to the ease of implementation and the better power utilization. it also gives a better signal-to-noise ratio because receiver equalization ampli?s both the signal and the noise at the receiver applying too much preemphasis when it is not required, for example when driving a short backplane path, will also degrade the data eye opening at the receiver. in the orspi4 the degree of transmit preemphasis can be pro- grammed with a two-bit control from the microprocessor interface as shown in table 28. the high-pass transfer function of the preemphasis circuit is given by the following equation, where the value of ? is shown in table 28. h(z) = (1 ?az ? ) (1) table 28. preemphasis settings receive path (backplane to fpga) logic the receiver section receives high-speed serial data at the external differential cml input pins. these data are fed to the clock recovery section which generates a recovered clock and retimes the data. therefore the receive clocks are asynchronous between channels. the retimed data are deserialized and presented as an 8-bit decoded or a 10-bit unencoded parallel data on the output port. the receiver also optionally recognizes comma characters, detects code violations and aligns the bit stream to the proper word boundary. pe1 pe0 amount of preemphasis (a) 0 0 0% (no preemphasis) 0 1 12.5% 1 0 12.5% 1 1 25% lattice semiconductor orca orspi4 data sheet 111 1036-pin ftsbga devices have been discontinued. as shown in figure 52, the basic blocks in the receive path include: receive serdes block cml input buffer receive pll 1:10 demultiplexer (demux) clock and data recovery (cdr) section 10b/8b decoder 1:4 demultiplexer and serdes/fpga interface 1:4 demux low speed parallel serdes/fpga logic interface multi-channel alignment logic figure 52. basic logic blocks, receive path, single channel (typical reference clock frequency) each channel provides its own received clock, received data and k-character detect signals to the fpga logic. incoming data from multiple channels can be aligned using comma (/k/) characters or /a/ character (as speci?d either in fibre channel speci?ations or in ieee 802.3ae for xaui based interfaces). if the 8b/10b decoders are bypassed, then 40-bit data streams are passed to the fpga logic. no channel alignment can be done in this 8b/10b bypass mode. refclkp refclkn refclk buffer mux rck78 78.125 mhz rcksel[0:1] logic common to quad from other 3 channels to other 3 channels from control register { { pll prbs checker cml buffer 1:10 demux 8b/10b encoder (with bypass) hdinp_x hdin_x cdr byte align rx serdes block xaui state machine 1:4 demux (x 10) 156.25 mhz fifo multi- channel alignment fpga logic backplane serial link rwckx 78.125 mhz multi-channel alignment block 78.125 mhz 78.125 mhz clock ralignx[3:0] align character detect 4 4 rwbit8x[3:0] 4 bits k-control 32 rwdx[31:0] 32-bit data rsys_clk_# 78.125 mhz 2:1 mux (x40) mrwdx[39:0] cv_selx 4 rwbit9x[3:0] 40 36 32-bit data 4 bits k-ctrl synchronization status bits fibre channel state machine srbd_x[0:9] demux block scvx 312.5 mhz clocks 10 2 sbytsync_x swdsync_x note: x= [a, ..., b] x# = [1, 2] 3 fpga logic lattice semiconductor orca orspi4 data sheet 112 1036-pin ftsbga devices have been discontinued. synchronization the orspi4 serdes rx logic performs four levels of synchronization on the incoming serial data stream. each level builds upon the previous, providing ?st bit, then byte (character), then channel (32-bit word), and ?ally multi- channel alignment. bit alignmen t is the task of the clock/data recovery (cdr) block. this block utilizes a pll that locks to the transi- tions in the incoming high-speed serial data stream, and outputs the extracted clock as well as the data. if the pll is unable to lock to the serial data stream, it instead locks to refclk to stabilize the voltage-controlled oscillator (vco), and periodically switches back to the serial data stream to again attempt synchronization. this process continues until a valid input data stream is detected and lock is achieved. the cdr can maintain lock on data as long as the input data stream contains an adequate data ?ye (i.e., jitter is within speci?ation) and the maximum data stream run length is not exceeded. byte alignment occurs once valid bit alignment is achieved. the byte aligner looks for a particular 7-bit sequence (either 0011111 or its complement, 1100000) that, has been 8b/10b encoded per fibre channel or ieee 802.3.2002 speci?ations, only occurs in the comma (/k/) characters k28.1, k28.5 and k28.7. byte alignment only occurs when the enbysync_x signal for that channel is active high, and re-alignment occurs on each 7-bit sequence encountered. however, if enbysync_x is asserted active high and no comma character is encoun- tered, and then is brought inactive low, the channel will still perform one byte alignment operation on the next comma character. byte alignment occurs immediately when an alignment sequence is detected, so the lock time is only one clock period. word (32-bit) alignment can occur after the fibre channel (xaui_mode_x = ?? or xaui (xaui_mode_x = ?? state machine has reached the in-synchronization state. in fibre channel mode, synchronization (wdsync_x = ?? will occur after three ordered sets of data have been received in the absence of any code violations. after this, the next ordered set will cause the output data to be aligned such that the comma character is in the most signi? cant byte. thus, 32-bit word alignment has been achieved when four ordered sets have been detected. the time required is directly dependent on comma-character density. once word alignment is accomplished, no further alignment occurs unless and until wdsync_x goes to zero and back to one again. comma characters that are not located in the most signi?ant byte position will not trigger fur- ther re-alignment while wdsync_x is active. this behavior is as de?ed by the fibre channel speci?ation. how- ever, it means that, if the channel experiences an abrupt delay change (as could occur if an external mux performs protection switch between two links) and if the delay change is close enough to a full character or characters that not enough code violations are generated to cause loss of wdsync_x, the channel could become misaligned and remain that way inde?itely. as mentioned above, this behavior is that de?ed by the fibre channel speci?ation. in xaui mode, as the state diagram later in this data sheet indicates, three error-free code-groups containing com- mas must be detected before synchronization is declared. multi (2 or 4) channel alignment (lane alignment in xaui mode) can be performed after 32-bit word alignment is complete. multi-channel alignment is described in later sections of this data sheet. receive cml input buffer and serdes the receiver section receives high-speed serial data at its differential cml input port. the receive input is an ac coupled input. the received data is sent to the clock recovery section which generates a recovered clock and retimes the data. valid data will be received after the receive pll has locked to the input data frequency and phase. the received serial data is converted to a 10-bit wide parallel data by the 1:10 demultiplexer. clock recovery is per- formed by the serdes block for each of the eight receive channels. this recovered data is then aligned to a 10-bit word boundary by detecting and aligning to a comma special character. word alignment is done for either polarity of the comma character. the 10-bit code word is passed to the 8b/10b decoder, which provides an 8-bit byte of data, a special character indicator bit and a sbytsync_x signal (where again x is a placeholder for a,...,d). data from a serdes channel is sent to the demux block in 10-bit raw form or 8-bit decoded form. accompanying this data are the comma-character indicator (sbytsync_x), link-state indicator (swdsync_x), clocks (srbc0_x, and srbc1_x), and code-violation indicator (scvx). the two internal clocks operated at twice the reference clock lattice semiconductor orca orspi4 data sheet 113 1036-pin ftsbga devices have been discontinued. frequency. with the 8b10br_x control bit of the serdes channel set to ?? the data presented at srbd_x[9:0] will be decoded characters. bit 8 will indicate whether srbdx[7:0] represents an ordinary data character (bit 8 = 0), or whether srbd_x[7:0] represents a special character, like a comma. bit 9 may be either a code violation indicator or one of seven out of synchronization state indicators, as described later. figure 53. receive path timing for a single serdes channel. (note: xx = a, b, c, or d) when 8b10br is set to ?? the data at srbd_x[9:0] will not be decoded. the xaui link-state machine should not be used in this mode of operation. when in xaui mode, the mux/demux looks for /a/ (as de?ed in ieee 802.3ae v.2.1) characters for channel alignment and requires the characters to be in decoded form for this to work 1:4 demultiplexer (demux) the 1:4 demux has to accumulate four sets of characters presented to it at the serdes receive interface and put these out at one time at the low-speed receive interface. another task of the 1:4 demux is to recognize the synchronizing event and adjust the 4-byte boundary so that the synchronizing character leads off a new 4-byte word. in fibre channel mode, this synchronizing character is a comma. this feature will be referred to as demux word alignment in other areas of this document. demux word alignment will only occur when the communication channel is synchronized. when there is no synchronization of the link, the 1:4 demux will continue to output 4-byte words at some arbitrary, but constant, boundary. there are 2 control register bits available for each channel for word alignment. they are dowdalgn_x and nowdalgn_x. the dowdalgn_x bit is positive edge triggered. writing a 0 followed by a ? to this register bit will cause the cor- responding demux to look for a new comma character and align the 32-bit word such that the comma is in the most signi?ant byte position. it is important that the comma is in the most signi?ant byte position since the multi- channel aligner looks for comma in the most signi?ant byte only. typically, it is not necessary to set the dowdalgn_x bit. when the link state machine loses synchronization (demuxwas_x register bit is 0), the demux block automatically looks for a new comma character irrespective of whether the dowdalgn_x bit is set or not. however, as discussed earlier, the comma character may become misaligned without the fibre channel link state machine indicating a loss of synchronization. in such cases, the dowdalgn_x bit must be toggled to force resynchronization. embedded core ..... ..... pqrs txyz srbdx[9:0] ..... ..... srbc0x srbc1x ..... sbytsyncx, svcx swdsyncx q 0 r 8 r 9 s 0 p 4 p 5 p 6 p 7 p 8 p 9 ..... p 0 p 1 p 2 p 3 r 2 r 3 r 4 r 5 r 6 r 7 s 1 s 2 s 3 s 4 p hdinx srbdx[9:0] 1-bit 10-bit ..... ..... latency = approx 23 clocks ..... lattice semiconductor orca orspi4 data sheet 114 1036-pin ftsbga devices have been discontinued. the nowdalgn_x bit is a level-sensitive bit. if it is a ?? then the demux does not dynamically alter the word boundary based on comma and swdsync_x output of the serdes. this might be useful if a channel were con- ?ured to bypass the multi-channel alignment fifo and raw 40-bits of data are directed from serdes to fpga. in fibre channel mode, the default setting (nowdalgn_x = 0) causes the word boundary to be set as soon as the serdes swdsync_x output is a ? and a comma character has been detected. the character that is the comma becomes the most-signi?ant portion of the demultiplexed word. when the serdes loses link synchroni- zation it will drop swdsync_x low. the demux will begin search for word alignment as soon as swdsync_x goes to ? again. the demux passes on to the channel alignment fifo block a set of control signals that indicate the location of the synchronizing event. ralign_x[3:0] are these indicators. if there is no link synchronization, all of the ralign_x[[3:0] bits will be zeros independent of synchronizing events that come in. when the link is synchronized, then the bit that corresponds to the time of the synchronization event will be set to a ?? the relationship between a time sequence of values input at srbdx[7:0] to the values output at rwd_x[39:0] is shown in figure 54. a paral- lel relationship exists between srbdx[8] and rwbit8_x[3:0] as well as between srbd_x[9] and rwbit9_x[3:0]. figure 54. receive demux block for a single serdes channel. (note: xx = a, b, c, or d) one clock per block of two or four channels, called rck78, is sent to the fpga. the control bits rcksel[a,b] are used to select the channel that is the source for these clocks. link state machines two link state machines are included in each serdes channel; one for xaui applications and a second for fibre channel applications. the fibre channel link state machine is responsible for establishing a valid link between the transmitter and the receiver and for maintaining link synchronization. the machine is initially in the loss of synchronization (los) state upon power-on reset. this is indicated by wdsync_x = 0. while in this state, the machine looks for a particular number of consecutive idle ordered sets without any invalid data transmission in between before declaring syn- chronization achieved. achievement of synchronization is indicated by asserting wdsync_x = ?? speci?ally, the machine looks for three continuous idle ordered sets without any misaligned comma character or any running dis- parity based code violation in between. in the event of any such code violation, the machine would reset itself to the pppppppp srbdxx[9:0] 10-bit 40-bit rwd_xx[31:24] rwd_xx[23:16] rwd_xx[15:8] rwd_xx[7:0] latency = 4 rsys_clk [a1,...,b2] clocks t 7-0 t 8 t 9 q 7-0 q 8 q 9 x 7-0 x 8 x 9 r 7-0 r 8 r 9 y 7-0 y 8 y 9 s 7-0 s 8 s 9 z 7-0 z 8 z 9 rwbit8_xx[3] rwbit9_xx[3] rwbit8_xx[2] rwbit8_xx[1] rwbit8_xx[0] rwbit9_xx[2] rwbit9_xx[1] rwbit9_xx[0] p 7-0 p 8 p 9 lattice semiconductor orca orspi4 data sheet 115 1036-pin ftsbga devices have been discontinued. ground state and start its search for the idle ordered sets again. a typical valid sequence for achieving link synchro- nization would be k28.5 d21.4 d21.5 d21.5 repeated three times. in the synchronization achieved state, the machine constantly monitors the received data and looks for any kind of code violation that might result due to running disparity errors. if it were to receive four such consecutive invalid words, the link machine loses its synchronization and once again enters the loss of synchronization state (los). a pair of valid words received by the machine overcomes the effect of a previously encountered code violation. los is indicated by the status of wdsync_x output which now transitions from ? to ?? los is also indicated by demuxwas_x status register bit. this bit is set to ? during loss of synchronization. at this point the machine attempts to establish the link yet again. figure 55 shows the state diagram for the fibre channel link state machine. figure 55. fibre channel link state machine state diagram xaui link synchronization function for each lane, the receive section of the xaui link state machine incorporates a synchronization state machine that monitors the status of the 10-bit alignment. a 10-bit alignment is done in the serdes based on a comma charac- ter such as k28.5. a comma (0011111 or its complement 1100000) is a unique pattern in the 10-bit space that can- not appear across the boundary between any two valid 10-bit code-groups. this property makes the comma useful for delimiting code-groups in a serial stream. this mechanism incorporates a hysteresis to prevent false synchroni- zation and loss of synchronization due to infrequent bit errors. for each lane, the sync_complete signal is disabled until the lane achieves synchronization. the synchronization state diagram is shown in figure 56. the xaui state machine does not have any control over the serdes byte aligner. it is the user s responsibility to control the byte aligner through software access of register map address 30800. los = 1 last ordered set received: vw rst link synchronization achieved (wdsync = 1) os cv os os os cv cv cv cv cv 1vw 1vw 1vw 2 vw 2 vw 2 vw a b c d e h g f loss of synchronization (wdsync_x = 0) lsm_enable + powerup_reset vw: valid word (a 4 character based word having no code violation) with at least cv: code violation (running disparity based on illegal comma position) os: idle ordered set (a 4 character based word having comma as the 1st character) 1vw: first valid word after a code violation two preceeding valid words 2vw: second valid word after a code violation lattice semiconductor orca orspi4 data sheet 116 1036-pin ftsbga devices have been discontinued. this state machine is modeled after draft ieee 802.3ae, version 2.1 but will also operate properly with version 4.1 implementations. table 29 and table 30 describe the state variables used in figure 56. note that it takes four idle ordered sets (ex: k28.5, dx.y, dx.y, dx.y) to bring the state machine from a loss-of-sync to a sync_acq d_1 state. instead, when back-to-back commas are used, it takes a total of ?e commas to achieve the same result as with idle ordered sets. table 29. xaui link synchronization state diagram notation?ariables table 30. xaui link synchronization state diagram?unctions variable description sync_status fail: lane is not synchronized (correct 10-bit alignment has not been established). ok: lane is synchronized. ok_noc: lane is synchronized but a comma character has not been detected in the past 200 code-groups. enable_cdet true: align subsequent 10-bit words to the boundary indicated by the next received comma. false: maintain current 10-bit alignment. gd_cg current number of consecutive cg_good indications. function description sync_complete indication that alignment code-group alignment has been established at the boundary indicated by the most recently received comma. cg_comma indication that a valid code-group, with correct running disparity, containing a comma has been received. cg_good indication that a valid code-group with the correct running disparity has been received. cg_bad indication that an invalid code-group has been received. no_comma indication that comma timer has expired. the timer is initialized upon receipt of a comma. lattice semiconductor orca orspi4 data sheet 117 1036-pin ftsbga devices have been discontinued. figure 56. xaui link synchronization state diagram reference clock requirements there is one pair of serdes reference clock inputs on the orspi4. the differential reference clock is distributed to all channels in the block. each channel has a differential buffer to isolate the clock from the other channels. the input clock is preferably a differential signal; however, the device can operate with a single-ended input. the input reference clock directly impacts the transmit data eye, so the clock should have low jitter. in particular, jitter compo- loss_of_sync sync_status <=fail enable_cdet <= true sync_complete reset comma_detect_1 enable_cdet <= false cg_bad cg_bad cg_comma cg_comma cg_bad comma_detect_2 comma_detect_3 cg_comma sync_aqc d_1 sync_aqc d_1a sync_status <= ok no_comma and cg_bad sync_status <= ok_noc cg_bad cg_comma sync_aqc d_2 sync_aqc d_3 sync_aqc d_4 sync_aqc d_2a sync_aqc d_3a sync_aqc d_4a gd_cg <= gd_cg + 1 gd_cg <= 0 cg_good cg_good x (gd_cg ! = 3) cg_bad cg_good x (gd_cg = 3) cg_good x (gd_cg ! = 3) cg_bad cg_good*(gd_cg=3) cg_good cg_bad cg_good x (gd_cg = 3) cg_good cg_good x (gd_cg ! = 3) cg_bad cg_bad cg_bad gd_cg <= 0 gd_cg <= 0 gd_cg <=gd_cg + 1 gd_cg <=gd_cg + 1 no_comma and cg_bad lattice semiconductor orca orspi4 data sheet 118 1036-pin ftsbga devices have been discontinued. nents in the dc to 5 mhz range should be minimized. the required electrical characteristics for the reference clock are given in table 71. note: in sections of this data sheet, the differential clocks are simply referred to as the reference clock as refclk. synthesized and recovered clocks the serdes block contains its own dedicated plls for transmit and receive clock generation. the user provides a reference clock of the appropriate frequency, as described in the previous section. the transmitter pll uses the refclk inputs to synthesize the internal high-speed serial bit clocks. the receiver plls extract the clock from the serial input data and retime the data with the recovered clock. the receive pll for each channel has two modes of operation - lock to reference and lock to data with retiming. when no data or invalid data is present on the hdinp_x and hdinn_x pins, the receive vco will not lock to data and its frequency can drift outside of the nominal ?50 ppm range. under this condition, the receive pll will lock to refclk for a ?ed time interval and then will attempt to lock to receive data. the process of attempting to lock to data, then locking to clock will repeat until valid input data exists. there is also a control register bit per channel to force the receive pll to always lock to the reference clock. the high-speed transmit and receive serial data links can run at 0.6 to 3.7 gbits/s, depending on the frequency of the reference clock and the state of the control bits from the internal transmit control register. the interface to the serializer/deserializer block runs at 1/10th the bit rate of the data lane. additionally, the mux/demux logic converts the data rate and bit-width so the fpga core can run at 1/4th this frequency, which gives a range of 15 to 92.5 mhz for the data in and out of the fpga. internal clock signals at the fpga/core serdes interface there are several clock signals de?ed at the fpga/serdes interface in addition to the external reference clock. all of the serdes clock signals are shown in figure 57 and are described following the paragraphs. figure 57. serdes clock signals (high-speed serial i/o also shown) refclkp, refclkn: these are the differential reference clocks provided to the orspi4 device as described earlier. they are used as the reference clock for both tx and rx paths. for operation of the serial links at 3.125 gbits/s, the reference clocks will be at a frequency of 156.25 mhz. rwck[a:d]: these are the low-speed receive clocks from the serdes to the fpga across the core-fpga interface. common logic channel a channel b channel d channel c rck78 tck78 rsys_clk_1 tsys_clk_a rwcka rwckb tsys_clk_b rwckc tsys_clk_c rsys_clk_2 tsys_clk_d rwckd refclk[p:n] 2 hdin[p:n] 2 hdout[p:n] hdin[p:n] 2 hdout[p:n] hdout[p:n] 2 hdin[p:n] 2 hdout[p:n] 2 hdin[p:n] 2 2 2 lattice semiconductor orca orspi4 data sheet 119 1036-pin ftsbga devices have been discontinued. these are derived from the recovered low-speed complementary clocks from the serdes blocks. rwck_a belongs to channel a, rwck_b belongs to channel b and so on. with a reference clock input of 156.25 mhz, these clocks operate at 78.125 mhz. rck78: these are muxed outputs of rwcka[a:d] and rwckb[b:d] respectively. with a reference clock input of 156.25 mhz, these clocks operate at 78.125 mhz. rsys_clk_[1:2] these clocks are inputs to the serdes. these are used by each channel as the read clock to read received data from the alignment fifo within the serdes. to guarantee that there is no over?w in the alignment fifo, it is an absolute requirement that the write and read clocks be frequency locked to 0 ppm. examples of how to achieve this are shown in the section on recommended board-level clocking. tck78: this is a muxed output from the core to the fpga across the core-fpga interface of one of the four transmit ser- des clocks operating at up to 92.5 mhz in the serdes. tsys_clk[a:d]: these clocks are inputs to the serdes from the fpga. these are used by each channel to control the timing of the transmit data path. to guarantee correct transmit operation, these clocks must be frequency locked within 0 ppm to tck78. list of operating modes serdes transmit and receive clock rates table 31 shows typical relationship between the data rates, the reference clock, the transmit tck78 clock and the receive rck78 clock. the selection of full-rate or half-rate for a given reference clock speed is set by bits in the transmit and receive control registers, and can be set on a per-channel basis. table 31. transmit data and clock rates mixing half-rate, full-rate modes when channel alignment is enabled, all receive channels within an alignment group should be con?ured at the same rate. for example, channels a and b, can be con?ured for twin alignment and full-rate mode, while channels c and d can be con?ured for half-rate mode. in quad alignment mode, all four channels must be con?ured in either half or full-rate mode. register settings for multi-channel alignment are described in a later section. besides taking in a tsys_clk_x from the fpga logic for each channel, the transmit path logic sends back a clock of the same frequency, but arbitrary phase. this clock, tck78, is derived from the mux block of one of the 2 chan- nels in its serdes block. the mux blocks provide the potential source for tck78 by a divide-by-4 of the serdes stbc311xs clock used in synchronizing the transmit data words in the stbc311x clock domain. the stbc311x clocks are internal to the core and are not brought across the core/fpga interface data rate reference clock tck78[a: b] and rck78[a:b] clocks rate of channel selected as clock source 0.6 gbits/s 60 mhz 15 mhz half 1.0 gbits/s 100 mhz 25 mhz half 1.25 gbits/s 125 mhz 31.25 mhz half 2.0 gbits/s 100 mhz 50 mhz full 2.5 gbits/s 125 mhz 62.5 mhz full 3.125 gbits/s 156 mhz 78 mhz full 3.7 gbits/s 185 mhz 92.5 mhz full lattice semiconductor orca orspi4 data sheet 120 1036-pin ftsbga devices have been discontinued. the receiver section receives high-speed serial data at its differential cml input port and sends it in to the clock and data recovery (cdr) block. the cdr block then generates a recovered clock (rwckx) and retimes the data. thus, the recovered receive clocks are asynchronous between channels. transmit clock source selection the tcksel[a:b] bit select the source channel of tck78. the selection of the source for tck78 is controlled by this bit as shown in table 32. table 32. tck78 source selection recommended transmit clock distribution for the orspi4 as an example of the recommended clock distribution approach, tsys_clk_[a:d] can be sourced by tck78 as shown in figure 58 if the transmit line rate are common for all four channels in a quad. figure 58. transmit clocking for a single block if the transmit line rate is mixed between half and full rate among the channels, then the scheme shown in figure 59 can be used. the ?ure shows tsys_clk_a and tsys_clk_b being sourced by tck78 and tsys_clk_c and tsys_clk_d being sourced by tck78/2 (the division is done in fpga logic). similar clocking would be used for quad b. tcksel0 tcksel1 clock source 0 0 channel a 1 0 channel b 0 1 channel c 1 1 channel c common logic channel a channel b channel d channel c refclk[p:n] 2 156.25 mhz tck78 tsys_clk_a tsys_clk_c tsys_clk_b tsys_clk_d fpga logic all clocks at 78.125 mhz four channels of 3.125 gbits/s outgoing serial data lattice semiconductor orca orspi4 data sheet 121 1036-pin ftsbga devices have been discontinued. figure 59. mixed rate transmit clocking for a single block receive clock source selection and recommended clock distribution in the receive path, one clock per bank of four channels, called rck78, is sent to the fpga logic. the control reg- ister bits rcksel[0:1] are used to select the clock source for these clocks. the selection of the source for rck78 is controlled by these bits as shown in table 33. table 33. rck78 source selection in the receive channel alignment bypass mode, the data and recovered clocks for the four channels are indepen- dent. the data for each channel are synchronized to the recovered clock from that channel. rcksel0 rcksel1 clock source 0 0 channel a 1 0 channel b 0 1 channel c 1 1 channel c common logic channel a channel b channel d channel c refclk[p:n] 2 100 mhz tck78 tsys_clk_a tsys_clk_c tsys_clk_b tsys_clk_d fpga logic two channels of 2.0 gbits/s (full-rate) outgoing serial data channel a selected as clock source 50 mhz 2 25 mhz two channels of 1.0 gbits/s (half-rate) outgoing serial data lattice semiconductor orca orspi4 data sheet 122 1036-pin ftsbga devices have been discontinued. figure 60. receive clocking for a single quad figure 61. receive clocking for mixed line rates multichannel alignment the alignment fifo allows the transfer of all data to the system clock. the multi-channel alignment block (figure 52) allows the system to be con?ured to allow the frame alignment of multiple, slightly varying, data streams. this optional alignment ensures that matching serdes streams will arrive at the fpga in perfect data synchronization. each channel is provided with a 24 word x 36-bit fifo. the fifo can perform two tasks: (1) to change the clock domain from receive clock to a clock on the fpga side, and (2) to align the receive data over 2, 4, or 8 channels. this fifo allows a timing budget of +/- 230.4 ns that can be allocated to skew between the data lanes and for transfer to the system clock. the input to the fifo consists of 36-bits of demultiplexed data, ralign_x[3:0], rwd_x[31:0], and rwbit8_x[3:0]. the four ralign_x bits are control signals, and can be the alignment character detect signals, indicating the pres- ence of a comma character in fibre channel mode and the /a/ character in xaui mode. the other 32 rwd_x bits are the 8-bit data bytes from the 8b/10b decoder. the alignment character, if present, is the msb of the data. the common logic channel a channel b channel d channel c refclk[p:n] 2 156.25 mhz rck78 rwcka rwckc rsys_clk_1 rsys_clk_2 fpga logic four channels of 3.125 gbits/s incoming serial data 78.125 mhz rwckb rwckd all recovered clocks at 78.125 mhz common logic channel a channel b channel d channel c refclk[p:n] 2 100 mhz rck78 rwcka rwckc rsys_clk_1 rsys_clk_2 fpga logic two channels of 2.0 gbits/s (full-rate) incoming serial data 25 mhz rwckb rwckd recovered clocks at 25 mhz or 50 mhz recovered clocks at 50 mhz two channels of 1.0 gbits/s (half-rate) incoming serial data lattice semiconductor orca orspi4 data sheet 123 1036-pin ftsbga devices have been discontinued. rwbit8_x indicates the presence of a km.n control character in the receive data byte. only rwbit8_x and rwd_x inputs are stored in the fifo. during alignment process, ralign[3]_x is used to synchronize multiple channels. if a channel is not in any alignment group, it will set the fifo-write-address to the beginning of the fifo, and will set the fifo-read-address to the middle of the fifo, at the ?st assertion of ralign[3]_x after reset or after the resync command. the orspi4 has a total of four serdes channels. the incoming data of these channels can be synchronized in several ways or can be independent of one another. two serdes channels can be aligned together. channel a and b and/or channel c and d can form a pair as shown in figure 62. alternately, all four serdes channels can be aligned together to form a communication channel with a bandwidth of 10 gbits/s as shown in figure 63. indi- vidual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. figure 62. twin channel alignment figure 63. alignment of serdes quad (4-channels) for every alignment group, there are both an ovfl and an oos status register bit. the ovfl bit is set when align- ment fifo over?w occurs. the oos bit is ?gged when the down counter in the synchronization algorithm has reached a value of 0 and alignment characters from all channels within an alignment group have not been received. xaui lane alignment function (lane deskew) in xaui mode, the receive section in each lane uses the /a/ code group to compensate for lane-to-lane skew. the mechanism restores the timing relationship between the four lanes by lining up the /a/ characters into a column. figure 64 shows the alignment of four lanes based on /a/ character. a minimum spacing of 16 code-groups implies that at least ?80 bits of skew compensation capability should be provided, which the orspi4 signi?antly exceeds. channel a channel b channel c channel d channel a channel b channel c channel d t 1 t 0 twin alignment of channels a and b twin alignment of channels c and d channel b channel c channel d channel a channel b channel c channel d channel a quad alignment of channels a. b, c and d t 0 lattice semiconductor orca orspi4 data sheet 124 1036-pin ftsbga devices have been discontinued. figure 64. deskew lanes by aligning /a/ columns serdes/fpga interface this block provides the data formatting and receive data and clock signal transfers between the serdes and the fpga logic. there are also control and status registers in the fpga portion of the chip, which contain bits to con- trol the receive logic and to record status. these are described in later sections of this data sheet and communi- cate with the core using the system bus. the demultiplexed, receive word outputs to the fpga are shown in figure 52. these are each 40 bits wide. there are four of these interfaces, one for each serdes channel. each consist of four groups of 10-bit data or four groups of decoded information depending on setting of 8b10br_x control register bits. each 10-bit group of decoded information includes 8 bits of data and a one-bit k_ctrl indicator derived from the received data, and a tenth bit of status information. the function of the tenth bit varies from group to group and includes code violation, out of synchronization (oos) indicators and the ch248_sync_x status bit. ch248_sync_x indicates the status of multi-channel alignment of channel x and is high when the count for the multi-channel alignment block reaches zero, regardless of whether or not multi-channel alignment is successful. the mapping of the 10-bit groups to the mrwd_x[39:0] bits output to the fpga logic is summarized in table 34 and table 35. the various functions of the bits that vary from channel to channel, i.e., bits 29 and 19, are also described in table 35. table 34. de?ition of bits of mrwdx[39:0] bit index 8b10br=0 8b10br=1 nochalgn[a:b]=1 cv_selx=0 nochalgn[a:b]=1 cv_selx=1 nochalgn[a:b]=0 cv_selx=1 39 bit 9 of 10-bit data 3 cv_a3, code violation, byte 3 ch24_syncx 38 bit 8 of 10-bit data 3 k_ctrl for byte 3 k_ctrl for byte 3 37 bit 7 of 10-bit data 3 bit 7 of byte3 bit 7 of byte3 36 bit 6 of 10-bit data 3 bit 6 of byte 3 bit 6 of byte 3 35 bit 5 of 10-bit data 3 bit 5 of byte 3 bit 5 of byte 3 34 bit 4 of 10-bit data 3 bit 4 of byte 3 bit 4 of byte 3 33 bit 3 of 10-bit data 3 bit 3 of byte 3 bit 3 of byte 3 32 bit 2 of 10-bit data 3 bit 2 of byte 3 bit 2 of byte 3 31 bit 1 of 10-bit data 3 bit 1 of byte 3 bit 1 of byte 3 30 bit 0 of 10-bit data 3 bit 0 of byte 3 bit 0 of byte 3 29 bit 9 of 10-bit data 2 cv_a2, code violation, byte 2 see table 35 28 bit 8 of 10-bit data 2 k_ctrl for byte 2 k_ctrl for byte 2 27 bit 7 of 10-bit data 2 bit 7 of byte 2 bit 7 of byte 2 26 bit 6 of 10-bit data 2 bit 6 of byte 2 bit 6 of byte 2 lane 0 k rrkrk rkkrkrrk a lane 1 k rrkrk rkkrkrrk a lane 2 k rrkrk rkkrkrrk a lane 3 k rrkrk rkkrkrrk a lane 0 k rrkrk rkkrkrrk a lane 1 k rrkrk rkkrkrrk a lane 2 k rrkrk rkkrkrrk a lane 3 k rrkrk rkkrkrrk a lattice semiconductor orca orspi4 data sheet 125 1036-pin ftsbga devices have been discontinued. table 35. de?ition of the status bits of mrwdx that vary for different channels the code violation signals will only be valid if the corresponding cv_selx = ?? (if 8b10br=0, cv_sel should also be zero. the cv_x_or signals are obtained by oring four code violation signals from the 1:4 demux block. these are primarily indicators of received signal quality, since a single code violation will not force a loss of sync 25 bit 5 of 10-bit data 2 bit 5 of byte 2 bit 5 of byte 2 24 bit 4 of 10-bit data 2 bit 4 of byte 2 bit 4 of byte 2 23 bit 3 of 10-bit data 2 bit 3 of byte 2 bit 3 of byte 2 22 bit 2 of 10-bit data 2 bit 2 of byte 2 bit 2 of byte 2 21 bit 1of 10-bit data 2 bit 1 of byte 2 bit 1 of byte 2 20 bit 0 of 10-bit data 2 bit 0 of byte 2 bit 0 of byte 2 19 bit 9 of 10-bit data 1 cv_a1, code violation, byte 1 see table 35 18 bit 8 of 10-bit data 1 k_ctrl for byte 1 k_ctrl for byte 1 17 bit 7 of 10-bit data 1 bit 7 of byte 1 bit 7 of byte 1 16 bit 6 of 10-bit data 1 bit 6 of byte 1 bit 6 of byte 1 15 bit 5 of 10-bit data 1 bit 5 of byte 1 bit 5 of byte 1 14 bit 4 of 10-bit data 1 bit 4 of byte 1 bit 4 of byte 1 13 bit 3 of 10-bit data 1 bit 3 of byte 1 bit 3 of byte 1 12 bit 2 of 10-bit data 1 bit 2 of byte 1 bit 2 of byte 1 11 bit 1 of 10-bit data 1 bit 1 of byte 1 bit 1 of byte 1 10 bit 0 of 10-bit data 1 bit 0 of byte 1 bit 0 of byte 1 09 bit 9 of 10-bit data 0 cv_a0, code violation, byte 1 vl (connected to ground) 08 bit 8 of 10-bit data 0 k_ctrl for byte 0 k_ctrl for byte 0 07 bit 7 of 10-bit data 0 bit 7 of byte 0 bit 7 of byte 0 06 bit 6 of 10-bit data 0 bit 6 of byte 0 bit 6 of byte 0 05 bit 5 of 10-bit data 0 bit 5 of byte 0 bit 5 of byte 0 04 bit 4 of 10-bit data 0 bit 4 of byte 0 bit 4 of byte 0 03 bit 3 of 10-bit data 0 bit 3 of byte 0 bit 3 of byte 0 02 bit 2 of 10-bit data 0 bit 2 of byte 0 bit 2 of byte 0 01 bit 1 of 10-bit data 0 bit 1 of byte 0 bit 1 of byte 0 00 bit 0 of 10-bit data 0 bit 0 of byte 0 bit 0 of byte 0 channel index bit index name description all 39 ch24_syncx multi-channel alignment attempt complete if 1 a 29 cv_a_or code violation in one or more of the received 10-bit groups for channel a a 19 sync2_1_oos dual channel synchronization of channels a and b not successful if 1 b 29 cv_b_or code violation in one or more of the received 10-bit groups for channel b b 19 sync4_oos quad channel synchronization of serdes not successful if 1 c 29 cv_c_or code violation in one or more of the received 10-bit groups for channel c c 19 sync2_2_oos dual channel synchronization of channels c and d not successful if 1 d 29 cv_ad_or code violation in one or more of the received 10-bit groups for channel d bit index 8b10br=0 8b10br=1 nochalgn[a:b]=1 cv_selx=0 nochalgn[a:b]=1 cv_selx=1 nochalgn[a:b]=0 cv_selx=1 lattice semiconductor orca orspi4 data sheet 126 1036-pin ftsbga devices have been discontinued. (los) state in the word alignment state machines. since these signals come from the demux block, if multi-chan- nel alignment is enabled, the code violation signals correspond to data that must still be multi-channel aligned. hence these signals provide advance noti?ation of detected violations in data that will appear at the core/fpga interface several clock cycles later. the exact number of clock cycles that the data is delayed depends on the skew between the incoming data for the different channels. multi-channel alignment clocking strategies for the orspi4 the data on the four channels serdes can be independent of each other or can be synchronized in several ways. for example, two channels within the serdes can be aligned together; channel a and b and/or channel c and d. alternatively, all four channels in a serdes quad can be aligned together to form a communication channel with a bandwidth of 10 gbits/s. individual channels within an alignment group can be disabled (i.e., powered down) with- out disrupting other channels. clocking strategies for these various modes are described in the following para- graphs. for dual alignment, both twins within a quad can be sourced by clocks that are different from the other channels, however each pair of serdes must have the same clock. the channel pair a and b is driven on the low-speed side by rsys_clk_1 and the channel pair c and d are driven on the low-speed side by rsys_clk_2. either rwcka or rwcab can be connected to rsys_clk_1, and either rwckc or rwckd can be connected to rsys_clk_2. a clocking example for dual alignment is shown in figure 65. figure 65. receive clocking for a dual alignment in a single quad common logic channel a channel b channel d channel c refclk[p:n] 2 156.25 mhz rck78 rwcka rwckc rsys_clk_1 rsys_clk_2 fpga logic two bidirectional channels of 3.125 gbits/s serial data rwckb rwckd all clocks at 78.125 mhz tck78 tsys_clk_a tsys_clk_b tsys_clk_c tsys_clk_d two bidirectional channels of 3.125 gbits/s serial data lattice semiconductor orca orspi4 data sheet 127 1036-pin ftsbga devices have been discontinued. for receive quad alignment, rsys_clk_1 and rsys_clk_2 can be tied together as shown in figure 66. figure 66. clocking for a quad receive clocking for a dual alignment in a single quad multi-channel alignment con?uration register settings for multi-channel alignment are shown in table 36. table 36. multi-channel alignment modes to align all 4 channels: fmpu_synmode_[a:d] = 01 fmpu_synmode_b[a:d] = 11 to align two channels: fmpu_synmode_[a:b] = 10 for channel a and b fmpu_synmode_[c:d] = 10 for channel c and d to enable/disable synchronization signal of individual channel within a multi-channel alignment group: fmpu_str_en_x = ? enabled fmpu_str_en_x = ? disabled where x is one of [a:d]. to resynchronize a multi-channel alignment group set the following bit to zero, and then set it to one: fmpu_resync4 for quad [a:d] fmpu_resync2_1 for twin channel [a:b] register bits fmpu_syncmode_xx[0:1] mode 00 no multi-channel alignment 10 twin channel alignment 01 quad channel alignment common logic channel a channel b channel d channel c refclk[p:n] 2 156.25 mhz rck78 rwcka rwckc rsys_clk_1 rsys_clk_2 fpga logic four bidirectional channels of 3.125 gbits/s serial data rwckb rwckd all clocks at 78.125 mhz tck78 tsys_clk_a tsys_clk_b tsys_clk_c tsys_clk_d lattice semiconductor orca orspi4 data sheet 128 1036-pin ftsbga devices have been discontinued. fmpu_resync2_2 for twin channel [c:d] to resynchronize an independent channel (resetting the write and the read pointer of the fifo) set the following bit to zero, and then set it to one: fmpu_resync1_x serdes multi-channel alignment sequence 1. follow steps 1 and 2 in the start up sequence described in a later section. 2. initiate a serdes software reset by setting the swrst bit to ? and then to ?? note that, any changes to the serdes con?uration bits should be followed by a software reset. 3. wait for 3 ms. refclk should be toggling by this time. during this time, con?ure the following registers. set the following bit in register 30820 xaui_mode_x - set to ? for xaui mode or keep the default value of 0 if the fibre channel state machine was selected. enable channel alignment by setting fmpu_synmode bits in registers 30811 fmpu_synmode_x. set to appropriate values for 2, or 4 alignment based on table 36. set rclksel and tcksel bits in registers 30821. rcksel - choose clock source for 78 mhz rck78 (table 33). tcksel - choose clock source for 78 mhz tck78 (table 32). send data on serial links. monitor the following status/alarm bits: monitor the following alarm bits in registers 30000, 30010, 30020, 30030,. lki-pll_x lock indicator. a ? indicates that pll has achieved lock. monitor the following status bits in registers 30804: xauistat_x - in xaui mode, they should be 10. monitor the following status bits in registers 30805 demuxwas_x - they should be ? indicating word alignment is achieved. ch248_syncx - they should be ? indicating channel alignment. this is cleared by resync. 4. write a ? to the appropriate resync register 30820. note that this assumes that the previous value of the resync bits are ?? the resync operation requires a rising edge. two writes are required to the resync bits: write a ? and then write a ?? it is highly recommended to precede a resync with a word alignment, especially in sit- uations where a disturbance in the receive serdes path can cause misalignment of data and oos indica- tions without bringing the fc/xaui state machine to a loss of sync state. a word alignment is achieved by writing a ? and then a ? to the appropriate dowdalignx bits in registers 30810. lattice semiconductor orca orspi4 data sheet 129 1036-pin ftsbga devices have been discontinued. clocking schemes and timing diagrams- serdes figure 67 shows a timing diagram for the transmit section of the serdes interface. setup and hold numbers at the interface are also show. similar timing diagrams are also shown for the receive serdes interface section in both channel alignment mode (figure 68), and channel bypass mode (figure 69). serdes align mode interface figure 67. data: tbit9[a:d][3:0], tcomma[a:d][3:0], twd[a:d][31:0] clock: tsys_clk[a:d] q 3.5/0.5 ns 1.5/0.5 ns d 2.5 / 1.3 ns fpga embedded core c 1.1/ 0.18 ns d delay ?4 serdes_clk 311 mhz 78 mhz tck78 3.0ns setup = 1.5 ns hold = - 0.8 ns delay note: delays represent average max/min values, not absolute values actual delay values are used by isplever clock buffer delay relative to data fpga clock tree lattice semiconductor orca orspi4 data sheet 130 1036-pin ftsbga devices have been discontinued. serdes receive interface in channel alignment mode figure 68. data: mrwd[a:d][39:0] clock: rsys_clk_1, rsys_clk_2 d 3.5/0.5 ns 1.5/0.5 ns d 2.2 / 0.51ns fpga embedded core c 1.41/ 0.20 ns q (includes ck to q) total prop = 3.6 / 0.75 ns delay delay note: delays represent average max/min values, not absolute values actual delay values are used by isplever clock buffer delay relative to data lattice semiconductor orca orspi4 data sheet 131 1036-pin ftsbga devices have been discontinued. serdes receive interface in channel bypass mode figure 69. data: mrwd[a:d][39:0] clock: rwck[a:d] test modes in addition to the operational logic described in the preceding sections, the serdes contains logic to support var- ious test modes - both for device validation and evaluation and for operating system level tests. the following sec- tions discuss two of the test support logic blocks, supporting various loopback modes, in addition to serdes characterization pins. loopback testing loopback testing is performed by looping back (either internal to the serdes, by con?uring the fpga logic or by external connections) transmitted data to the corresponding receiver inputs, or received data to the transmitter out- put. the loopback path may be either serial or parallel. in general, loopback tests can be classi?d as ?ear end or ?ar end? in ?ear end loopback (figure 70(a)), data is generated and checked locally, i.e. by logic on, or connection of, test equipment to the same card as the fpsc. in ?ar end loopback (figure 70(b)), the generating and checking functions are performed remotely, either by test equipment or a remote system card. d 2.5 / 0.7 ns fpga embedded core 1.4/ 0.4 ns q total prop = 3.4 / 0.85 ns note: delays represent average max/min values, not absolute values ? rck78[a:d] c rwck[a:d] recovered 311mh z _serdes_clk delay delay delay actual delay values are used by isplever lattice semiconductor orca orspi4 data sheet 132 1036-pin ftsbga devices have been discontinued. figure 70. ?ear end vs. ?ar end loopback. (note: xx = a, b, c, or d) the loopback mode can also be characterized by the physical location of the loopback connection. there are two possible loopback modes supported by the serdes logic: high-speed serial loopback at the cml buffer interface (near end) parallel loopback at the serdes boundary (far end) these two loopback modes are described in more detail in the following sections. as noted earlier, other special- ized loopback modes can be obtained by con?uration of the fpga logic or by connections external to the fpsc. high-speed serial loopback at the cml buffer interface the high-speed serial loopback mode has the serial transmit signals looped back internally to the serial receive cir- cuitry. the internal loopback path is from the input connection to the transmit cml buffer to the output connection from the receive cml buffer. the data are sourced on the twdx[31:0], tcommax[3:0] and tbit9x[3:0] signal lines and received on the mrwdx[39:0] signal lines. the serial loopback path does not include the high-speed input and output buffers. if testen_x is set, the hdoutp_x and hdoutn_x outputs are active in this mode while the cml input buffers are powered down. the device is otherwise in its normal mode of operation. this mode is normally used for tests where the data source and destination are on the same card and is the basic loopback path shown in table 37. the data rate selection bits, txhr and rxhr, in the channel con?uration registers must be con?ured to carry the same value. table 37 summarize the settings of the control interface register con?uration bits for high-speed serial loopback. device under test (dut) cml buffer cml buffer hdin[p:n]_xx 2 non-functional embedded core fpga logic 40 mrwdxx[39:0] 32 4 4 receive transmit twdxx[31:0] tcommaxx[3:0] tbit9xx[3:0] hdout[p:n]_xx 2 data checking data generation n m active (to eye diagram measurement or remote system card) test equipment or logic on local system card (a) ?ear end loopback high speed serial loopback connection device under test (dut) data generation data checking 2 2 hdin[p:n]_xx hdout[p:n]_xx n m non-functional active (to logic on local system card) (b) ?ar end loopback fpga logic 40 mrwdxx[39:0] receive 4 4 transmit twdxx[31:0] tcommaxx[3:0] tbit9xx[3:0] 32 de mux 8b/10b serdes cml buffer 8b/10b cml buffer serdes block parallel loopback connection serdes embedded core test equipment or logic remote system card lattice semiconductor orca orspi4 data sheet 133 1036-pin ftsbga devices have been discontinued. table 37. high-speed serial loopback con?uration bit de?itions for the serdes parallel loopback at the serdes boundary in this parallel loopback, differential data are received at the hdinp_x and hdinn_x pins and are retransmitted at the hdoutp_x and hdoutn_x pins. the loopback path is at the interface between the serdes blocks and the mux and demux blocks and uses the parallel 10-bit buses at these interfaces (see figure 70b). the loopback connection is made such that the input signals to the tx serdes block is the same as the output signals from the rx serdes block. in this parallel loopback mode, the mrwdx[39:0] signal lines remain active and the twdx[31:0], tcommax[3:0] and tbit9x[3:0] signal lines are not used. this mode is normally used for tests where serial test data is received from and transmitted to either test equipment or via a serial backplane to a remote card and is the basic loopback path shown earlier in figure 70(b). the data rate selection bits txhr and rxhr in the channel con?uration registers must be con?ured to carry the same value. also, the 8b/10b encoder and decoder are excluded from the loopback path by setting the 8b10bt and 8b10br con?uration bits to ?? table 38 illus- trates the control interface register con?uration for the parallel loopback. table 38. parallel loopback at the serdes boundary con?uration bit de?itions for the serdes serdes characterization test mode the serdes characterization mode is a test mode that allows for direct control and observation of the transmit and receive serdes interfaces at chip ports. with these modes the serdes logic and i/o can be tested one channel at a time in either the receive or transmit modes. the serdes test mode requires that the serdes block be selected instead of the spib block during the module generation phase of the orspi4 in isplever . in addition, the testmd[1:0]n signals need to be set to ? during serdes characterization. register address bit value bit name comments 30002, 30012, 30022, 30032 bit 0 = 0 or 1 txhr set to ? or ?? txhr and rxhr bits must be set to the same value. bit 7 = 0 or 1 8b10bt set to ? or ?? if set to ?? the 8b/10b encoder is excluded from the loopback path. the 8b/10b encoder and decoder selection con- trol bits must both be set to the same value. 30801 bit 0 = 1 (channel a) bit 1 = 1 (channel b) bit 2 = 1 (channel c) bit 3 = 1 (channel d) loopenb_xx set any of the bits 0-3 to ? to do serial loopback on the corre- sponding channel.* the high-speed serial outputs will not be active. *this test mode can also be set using testen_xx in place of loopenb_xx. in that case, test mode must be set to 00000. register address (hex) bit value bit name comments 30002, 30012, 30022, 30032 bit 0 = 0 or 1 txhr set to ? or ?? txhr and rxhr bits must be set to the same value. bit 7 = 0 8b10bt set to ? the 8b/10b encoder is excluded from the loopback path. the 8b/10b encoder and decoder selection control bits must both be set to ?? 30003, 30013, 30023, 30033 bit 0 = 0 or 1 rxhr set to ? or ?? txhr and rxhr bits must be set to the same value. bit 3 = 0 8b10br set to ?? the 8b/10b decoder is excluded from the loopback path. the 8b/10b encoder and decoder selection control bits must both be set to ?? 30005 bit 7 = 1 gtesten set to ? if the loopback is done globally on all four channels. 30006, 30016, 30026, 30036 bits[4:0] testmode set to 00001 lattice semiconductor orca orspi4 data sheet 134 1036-pin ftsbga devices have been discontinued. the serdes characterization test mode is con?ured by setting bits in the control registers via the system bus. the transmit characterization test mode is entered when schar_ena= ? (address 30830, bit 4) and schar_txsel= ? (address 30830, bit 5). entering this mode will cause chip port inputs to directly control the serdes low-speed transmit ports of one of the channels as shown in table 39. table 39. serdes transmit characterization mode the x in the table represents a single channel in the serdes quad, selected by the schar_chan control bits (address 30830, bits 6 and 7). the decoding of schar_chan is shown in table 40. table 40. decoding of schar_chan the receive characterization test mode is entered as long as testmd[1:0]n = 00. in this mode, one of the chan- nels of serdes outputs is observed at chip ports as shown in table 41. the channel that is observed is also based on the decoding of schar_chan as shown in table 40. the receive characterization pins can be observed independently, whether the transmit characterization pins are enabled or not. table 41. serdes receive characterization mode required inputs inputs used during mode testmd[1:0]n=00, schar_en=1, schar_txsel=1 tbcx (transmit) pmia15 ldin9x pmia14 ldin8x pmia13 ldin7x pmia11 ldin6x pmia9 ldin5x pmai8 ldin4x pmia7 ldin3x pmia6 ldin2x pmia5 ldin1x pmia4 ldin0x pmia2 schar_chan0 schar_chan1 channel 00a 10b 01c 11d required inputs outputs used during mode testmd[1:0]n=00 tbc311 pmid20 cv pmid21 bytsync pmid22 wdsync pmid23 rbco pmid24 rbc1 pmid25 ldout9 pmid26 ldout8 pmid 27 ldout7 pmid28 ldout6 pmid29 ldout5 pmid30 ldout4 pmid31 ldout3 pmid32 ldout2 pmid33 ldout1 pmid34 ldout0 pmid35 lattice semiconductor orca orspi4 data sheet 135 1036-pin ftsbga devices have been discontinued. memory controller functional description the orspi4 device includes a memory controller interface to an external second generation quad data rate (qdrii) memory. this is provided for additional data buffering beyond the embedded dprams. in this case, the embedded dprams are used as clock-crossing domain fifos. the key requirement for this memory interface is the support of a throughput of greater than 20 gbits/s so that all the data received on the spi4 interface at 10 gbits/s can be buffered. a qdrii sram supports this throughput with 32 unidirectional data lines. a 36-bit inter- face is provided to allow for parity or control bits to be added. the controller block provides the ability to access an external qdrii sram through the fpga. a set of 72 input data and 72 output data signals are available across the core-fpga interface. of the 72 signals, eight can be used either for parity or for data. the core passes the data transparently to and from the qdrii sram in two-word or four-word bursts. the data interfaces to memory are 36 bits wide and the address bus is 18 bits wide. this supports the interfaces required for a 512k x 36 bit (18 mbit) qdrii sram. the basic blocks of the memory controller are: fifos for write data and instructions fifos for read data and instructions read and write controllers (including fifo and memory interface state machines) address multiplexer (mux) write data demux and read data capture/mux blocks a logical block diagram of the memory controller is shown in figure 71. details of the individual blocks are outlined in the following sections. the blocks are described in sequence for a write from the fpga and a subsequent read to the fpga. figure 71. orspi4 qdrii memory controller block diagram. write data fifo read data fifo read instruction fifo write instruction fifo full full full empty 74 32 32 72 write controller read controller address mux write data demux read data mux/ capture 72 72 36 36 18 18 18 read clock write clock empty re empty re empty re we full fpga logic qdrii sdram clock select #1 pll cout = cin * n/m clock select #2 mcrefclk atrefclk btrefclk cout = cin / 2 write enable read enable enable enable we we we re 74 32 32 pmic w# r# q cq sa d k f_mc_refclk mc_sysclk f_mc_wd mc_wdfifo_full f_mc_wdfifo_we f_mc_wclk f_mc_wi mc_wififo_full f_mc_wififo_we f_mc_ri mc_rififo_full f_mc_rififo_we f_mc_rclk mc_rd mc_rdfifo_empty f_mc_rdfifo_re pmiq pmia pmiwn pmik pmirn pmid fpga_reset_mc orspi4 qdr ii core orspi4 device external memory 2 rst rst rst rst rst rst rst rst rst lattice semiconductor orca orspi4 data sheet 136 1036-pin ftsbga devices have been discontinued. fpga/memory controller core interface description table 42 lists the signals at the fpga/core interface for the memory controller block. table 42. fpga/embedded core signals memory controller - detailed description write data and instruction fifos the write data fifo (wdfifo) stores data written into it by logic in the fpga. the con?uration is 64 by 74 bits. read/write pointers and ?l-level logic is included. the fifos also function as an asynchronous clock domain boundary between the fpga generated write clock and the memory controller (mc) system clock (mc_sysclk). writes from the fpga that are asynchronous to the memory clock (k, k#) are allowed. it is also possible to run the fifo in synchronous mode by looping back the 1x clock via the fpga to the fifo write clock (mc_wclk). a set of 72 data signals is available across the core-fpga interface. of the 72, eight signals can be either used for parity or data. the core, however, passes the data transparently to the qdrii sram. data length is speci?d in terms of fifo lines. if data length is > 64 fifo lines, then the user must segment the data. the write instruction fifo (wififo) is con?ured 4 by 32 bits respectively, in order to store up to 4 instructions that are written to the mc by logic in the fpga. the instruction ?lds are id (data/address coherency), data length (number of cache lines) and address (for qdr memory). write instruction and data word formats are shown in fig- ure 72. signal direction from /to description qdrii sram read/write control f_mc_wd[73:0] fpga core write data to memory controller write data fifo f_mc_wi[31:0] fpga core write instruction to memory controller read instruction fifo mc_rd[71:0] core fpga read data from memory controller read data fifo f_mc_ri[31:0] fpga core read instruction to memory controller write instruction fifo mc_wdfifo_full core fpga full ?g from mc write data fifo. full threshold is set by the mc_full_threshold register bits. mc_wififo_full core fpga full ?g from mc write instruction fifo. mc_wififo_full high indicates that only one more instruction can be written to the instruction fifo. mc_rdfifo_empty core fpga empty ?g from mc read data fifo. empty threshold is set by the mc_empty_threshold register bits. mc_rififo_full core fpga full ?g from mc read instruction fifo. mc_rdfifo_full high indicates that only one more instruction can be written to the instruction fifo. f_fmc_wdfifo_we fpga core write enable to write data fifo f_fmc_wififo_we fpga core write enable to write instruction fifo f_fmc_rdfifo_re fpga core read enable to read data fifo f_fmc_rififo_we fpga core write enable to read instruction fifo f_mc_wclk fpga core memory controller write clock f_mc_rclk fpga core memory controller read clock mc_sysclk core fpga internal system clock for the memory controller i/f f_mc_refclk fpga core memory controller reference clock fpga_reset_mc fpga core memory controller asynchronous soft reset lattice semiconductor orca orspi4 data sheet 137 1036-pin ftsbga devices have been discontinued. figure 72. write data and instruction word formats the user starts a write cycle by writing data to the wdfifo. the maximum data length is 63 lines deep and the minimum is one 72-bit data word (or one line). the user provides the instruction word associated with a data string during the write period for the last word of the data. this sequence can continue to repeat as long as the mc_wxfifo_full ?gs from the embedded core remain inactive. once the mc_wififo_full ?g is asserted, the user may send data words to the wdfifo locations (assuming the mc_wdfifo_full ?g has not been asserted) and write one last instruction word to the instruction fifo as the last data word is written into the data fifo. the timing diagram for the write interface for a typical write sequence is shown in figure 73. the write sequence in this case consists of writing 32 words to location a0 followed by one word each to locations a1, a2, a3 and a4. the mc_wififo_full is asserted after the instruction for location a2 has been written, indicating that only one more instruction may be written to the instruction fifo. the write to location a4 cannot occur until the mc_wififo_full ?g is deasserted. the mc_wdfifo_full ?g remains low in this case since the full thresh- old for the data fifo has not been reached figure 73. orspi4 memory controller interface to fpga ?write timing diagram in the ?st clock cycle, the ?st word of the data burst is written along with the id bit value of 00. the instruction word is updated on the last word of a data burst and contains the id bit value, address and length of the data burst. the maximum burst length is set by the depth of the data fifo, which is 64 fifo lines. the data length in the address data length 0 17 18 24 30 31 write instruction word 0 71 72 73 write data id bits write data word 29 23 27 28 reserved i d bits reserved f_mc_wclk f_mc_wdfifo_we f_mc_wd(73:72) f_mc_wd(71:0) f_mc_wififo_we f_mc_wi(25:24) f_mc_wi(23:18) f_mc_wi(17:0) mc_wififo_full 00 01 10 11 00 d0-0 ... d0-31 d1-0 d2-0 d3-0 d4-0 00 01 10 11 00 a0 a1 a2 a3 a4 d*1 d*1 d*1 d*1 d*32 lattice semiconductor orca orspi4 data sheet 138 1036-pin ftsbga devices have been discontinued. instruction word is provided in terms of fifo lines. data length for data associated with a0 is shown to be 32 lines. the maximum burst length is set by the depth of the data fifo which is 64 fifo lines. data is presented as 9 bytes in every mc_wclk cycle. a new data word always begins at bit position 71 and has a unique 2-bit id. the transition from one id value to another indicates the start of a new data burst as shown in figure 72. for each burst, the values of the id ?lds in the data word and the instruction word are compared. the write controller ?st waits for the empty ?g from the instruction fifo to be deasserted and processes the ?st pending instruction. the core reads the instruction word ?st. based on the data length, the core starts to read the appropriate amount of data from the data fifo. the address and data length are passed to the write controller state machine. after the last data word has been read from the data fifo, the core increments the instruction fifo address to the next pending instruction. the 2-bit id ?ld in each data word is compared to the 2-bit id ?ld in the processed instruction to maintain data/instruction coherency. if the id ?lds in the data and instruction words do not match, an error is sent to a soft- ware register bit. it is the responsibility of the fpga to provide the exact amount of data speci?d in the data length ?ld of the instruction word. a programmable fifo full ?g (mc_wdfifo_full) is available to the fpga for the data fifo. the fifo ?g threshold is set by the 4-bit software register ?ld mc_full_threshold. if the mc_wdfifo_full ?g is pro- grammed to indicate a truly full condition, the fpga logic must assure that the fifo does not overrun and that an instruction word is written in parallel with the ?al data word of a sequence. address multiplexer (mux) address information to the qdrii sram is multiplexed between the write port and the read port. this is possible since data is always transferred in two-word or four-word bursts (word is 36-bits). logic in the sram supplies the address least signi?ant bits for the two-word burst case and the lower two lsbs in the case of four-word bursts. it is however, necessary to make sure read and write addresses do not contend for the address bus. this function is performed by the address mux logic based on signals from the memory read controller (mrc) and memory write controller (mwc). figure 74 and figure 75 show the timing of signals at the qdrii sram interface for two-word and four-word reads and writes. the burst size is selectable through the ?ld mc_burst_mode in the con?uration registers 30b03[0]. write data is sent on the ?st rising edge of the positive clock signal (k), after the write address is pro- vided. read data is returned on the second rising edge of k, after the read address is provided. if a sequence of read and write addresses is sent, both read data and write data are available simultaneously. it is this feature that gives the qdrii sram its high throughput. note: except for one address signal, there is no requirement that pmia address signals be connected to a particu- lar address input on the qdrii sram, since writes and reads share the one and only address bus. the only excep- tion is pmia17, which is only used in 2-word mode, and thus must be connected to the corresponding qdrii sram address input that is only present on the 2-word device (if 2-word/4-word compatibility is to be maintained). flexibility in assigning these signals can be useful in optimizing the layout of this bus. lattice semiconductor orca orspi4 data sheet 139 1036-pin ftsbga devices have been discontinued. figure 74. . orspi4 memory controller interface to qdrii: 4-word burst mode figure 75 shows the timing of signals at the qdrii sram interface for two-word reads and writes. in this case, address data is sent on both the rising and falling edges of the positive clock signal. write data is sent on the ?st rising edge of k before the write address and second data word are provided on the falling edge. as in the four- word case, read data is returned on the second rising edge of k after the read address is provided (on a rising edge of the positive clock). figure 75. orspi4 memory controller interface to qdrii: 2-word burst mode r1 r2 w1 w2 w1a w1b w1c w1d w2a w2b w2c w2d r1a r1b r1c r1d r2a r2b r1 w1 r2 w2 r2c r2d k k# r# w# sa d q k k# r# w# sa d q r1 r3 w2 w4 w1a w1b w2a w2b w3a w3b w4a w4b r1a r1b r2a r2b r3a r3b r1 r2 r3 r4 r4a r4b r2 r4 w1 w3 w1 w2 w3 w4 lattice semiconductor orca orspi4 data sheet 140 1036-pin ftsbga devices have been discontinued. write controller and write data demux the write timing shown in figure 74 and figure 75 is generated by the memory write controller (mwc) logic based on instruction and status signals from the write fifos and synchronization information from the memory read controller (mrc). the mwc has two functions. first it will read the instruction words from the instruction fifo and separate the bit ?lds into address, id and data length. then it will generate write cycle timing based on the type of memory con?ured (2 or 4 word burst). the mwc will also do data/instruction data coherency (id) checking and generate an error (output mc_id_status) if the test fails. the write controllers run at 2x the clock rate (mclckx2) in order to generate the qdrii sram data and address timing correctly in relation to the differential memory clock (k, k#). the mwc must also arbitrate with the mrc to ensure that there is no contention between sram read and write cycles, as dis- cussed in the previous section. the mwc generates enables to initiate burst writes. separate read and write address counters are required and are loaded by the controllers with the content of the address ?ld in the instruction word. in order to support 512k x 36 ram in 2-word burst mode, 18 active address lines are required, whereas in 4-word burst mode, 17 are required. data to the qdrii sram must also be demultiplexed (demux) by the write data demux block in order to convert from the mc internal format of 72 bit buses to the 36-bit ddr format for the qdr sram. read data capture, mux and read controller the read timing shown in figure 74 and figure 75 is generated by the memory read controller (mrc) logic, based on information from the read instruction fifo. the mrc has two functions. first it will read the instruction words from the instruction fifo and separate the bit ?lds into address and data length information. then it will generate read cycle timing, based on the type of memory con?ured (2 or 4 word burst) and provide synchronization infor- mation to the memory write controller (mwc). the read controller generates enables to initiate the read cycle. a separate read address counters is required and is loaded by the controller with the content of the address ?ld in the instruction word. as was true with the mwr, to support 512k x 36 ram in two word burst mode, 17 active address lines are required, whereas in 4-word burst mode, 18 are required. data from the qdr ram must also be multiplexed (mux) in order to convert to the mc internal format of 72 bit buses from the 36-bit ddr format for the qdrii sram. in order to capture the sram read data the echo clocks (cq, cq#) generated by the sram are used to latch the data. this is the most robust and ?xible of schemes available to capture the data, as with this source synchronous technique, the impact of round trip delays from the data leaving the memory controller, to data being received back can be minimized. the outputs of the capture latches are retimed back into the mclk2x domain in order to be writ- ten to the read data fifo (rdfifo) discussed in the next section. read data and instruction fifos the read data fifo (rdfifo) is used to store the data that is returned from the qdrii sram. it is asynchro- nously read by logic in the fpga. the rdfifo size is 64 x 72 bits. the read instruction fifo (rififo) is similar to the wififo and is con?ured 4 by 32 bits respectively in order to store up to 4 instructions that are written to the mc by logic in the fpga. the instruction ?lds are data length (number of cache lines to read) and address (for qdr memory). the read instruction and data word formats are shown in figure 76 and figure 77 respectively. lattice semiconductor orca orspi4 data sheet 141 1036-pin ftsbga devices have been discontinued. figure 76. read data and instruction word formats figure 77. orspi4 memory controller interface to fpga ?read timing diagram the user can write/read instructions into the read instruction fifo as long as the mc_rififo_full ?g is low. if this ?g is high, the fifo can accept one more instruction. the user can start reading data from the read data fifo once the mc_rfifo_empty ?g goes low. it is the responsibility of the user to: maintain count of data from the read data fifo and check if they match the data length provided in the corre- sponding instruction word associate the data received with the address. data will be received in the same order as they were requested. the timing diagram for the read interface for a typical read sequence is shown in figure 77. the read sequence in this case consists of reading 2 words from location a0 followed by one word each from locations a1, a2, eight words from a3 and one word from a4 and a5. the mc_rififo_full is asserted after the instruction for location a2 has been written, indicating that only one more instruction may be written to the instruction fifo. the read instruction write to access location a4 cannot occur until the mc_rififo_full ?g is deasserted. the mc_rdfifo_empty ?g remains high until data has been read from the qdrii sram and is available to the fpga logic. 71 0 read data read data word address 0 17 data length 18 23 31 read instruction word 24 reserved (low) f_mc_rclk f_mc_rififo_we f_mc_ri(23:18) f_mc_ri(17:0) mc_rififo_full mc_rdfifo_empty f_mc_rdfifo_re mc_rd(71:0) d4*1 d0*2 d1*1 d2*1 d3*8 a4 a0 a1 a2 a3 d0-1 d1-0 d2-0 d0-0 d1-0 d1-0 lattice semiconductor orca orspi4 data sheet 142 1036-pin ftsbga devices have been discontinued. a programmable fifo empty ?g (mc_rdfifo_empty) is available to the fpga for the data fifo. the fifo ?g threshold is set by the 4-bit software register ?ld mc_empty_threshold. memory controller instruction latency an example of the instruction latency through the qdr ii memory controller for write instructions is shown in fig- ure 78. for this example, it is assumed that the clock from the fpga logic to the memory controller (f_mc_wclk) is synchronized to the k clock to the external memory. if these clocks are not synchronous, then the latency may vary. figure 78. orspi4 qdr ii memory controller ?fpga to external memory latency example the latency for read instructions is the same given the same clock relationship conditions. memory controller status reporting the following status or alarms will be reported to the user through software register bits: data length mismatch from the write controller state machine. this alarm bit will be set if a block of data read from the write data fifo does not match the data length from its associated instruction. data-instruction coherency error. this alarm bit will be set if the id ?ld in write data and its associated write instruction do not match. write data, read data fifo overrun and underrun errors. clocking schemes and timing diagrams- memory controller the memory controller unit requires three clocks: mc_wclk from the fpga, which controls the fpga-side accesses to the write instruction and write data f_mc_wclk = external memory k clock f_mc_wdfifo_we f_mc_wd(73:72) f_mc_wd(71:0) f_mc_wififo_we f_mc_wi(25:24) f_mc_wi(23:18) f_mc_wi(17:0) external memory w# 00 d0-0 ... d0-31 00 a0 d*32 w1 2 k clock cycles instruction latency external memory k clock internal fpga logic to memory controller interface orspi4 to external memory interface lattice semiconductor orca orspi4 data sheet 143 1036-pin ftsbga devices have been discontinued. fifos (figure 71). mc_rclk from the fpga, which controls the fpga-side accesses to the read instruction and read data fifos. the main clock for the unit is selected by mc_ick_sel (con?uration register 30b03[2:3]) which controls all remaining clocking, including the clocks supplied to the external qdr-ii sram. this clock can be sourced as fol- lows: mc_ick_sel = 0 selects the dedicated memory controller external clock input mcrefclk = freq_in mc_ick_sel = 1 selects the spia unit's external clock atrefclk = freq_in; mc_ick_sel = 2 selects the spib unit's external clock btrefclk = freq_in, or mc_ick_sel = 3 selects the fpga-supplied signal f_mc_refclk= freq_in. the above-selected clock, can then be modi?d in frequency, by mc_ock_sel (con?uration register 30b03[7]) as follows: mc_ock_sel = 0 selects a pll, such that freq_out = (freq_in * (pll_n + 1)/(2 * (pll_m + 1))); or mc_ock_sel = 1 selects a divide-by-2, such that freq_out = (freq_in / 2). the pll_n value is obtained from the con?uration register 30b04[1:3]. pll_m value is obtained from con?u- ration register 30b04[5:7]. at the right side of the four internal fifos in figure 71, the data is transferred as two 36-bit words per freq_out clock cycle, but is then time-multiplexed into a single 36-bit ddr bus operating at frequency (freq_out * 2) for transfer to the external qdr-ii sram. the clock supplied to the qdr-ii sram is at frequency freq_out. figure 79 through figure 85 show the timing diagrams for the embedded controller/fpga interface. figure 79. data: f_mc_wd[73:0], f_mc_wi[31:0], f_mc_ri[31:0] clock: f_mc_wclk q 3.5/0.5 ns 1.5/0.5 ns fifo delay d 2.4/ 0.75 ns fpga embedded core c 1.1/ 0.74 ns setup= 1.6 ns hold = 0.3 ns note: delays represent average max/min values, not absolute values delay actual delay values are used by isplever clock buffer delay relative to data lattice semiconductor orca orspi4 data sheet 144 1036-pin ftsbga devices have been discontinued. figure 80. f_mc_ri[31:0] clock: f_mc_rclk figure 81. f_mc_wififo_we, f_mc_wdfifo_we clock: f_mc_wclk q 3.5/0.5 ns 1.5/0.5 ns fifo d 2.4/ 0.75 ns fpga embedded core c 1.35/ 0.85 ns setup = 1.4 ns hold = 0.4 ns note: delays represent average max/min values, not absolute values delay delay actual delay values are used by isplever clock buffer delay relative to data setup = 1.4 ns hold = 0.4 ns q 3.5/0.5 ns 1.5/0.5 ns fifo d 2.7/ 0.73 ns fpga embedded core c 1.7/ 0.75 ns setup= 2.8 ns hold = 0.37 ns delay delay note: delays represent average max/min values, not absolute values actual delay values are used by isplever clock buffer delay relative to data lattice semiconductor orca orspi4 data sheet 145 1036-pin ftsbga devices have been discontinued. figure 82. f_mc_rdfifo_re, f_mc_rififo_we clock: f_mc_rclk figure 83. data: f_mc_rd[71:0] clock: f_mc_rclk q 3.5/0.5 ns 1.5/0.5 ns d 2.5/ 0.76 ns fpga embedded core c 1.92/ 0.85 ns setup= 2.0 ns hold = 0.45 ns dq delay delay note: delays represent average max/min values, not absolute values actual delay values are used by isplever clock buffer delay relative to data d 3.5/0.5 ns 1.5/0.5 ns d 1.36 / 0.38 ns fpga embedded core c 1.94/ 0.83 ns q total prop = 3.6 / 1.3 ns delay delay note: delays represent average max/min values, not absolute values actual delay values are used by isplever clock buffer delay relative to data lattice semiconductor orca orspi4 data sheet 146 1036-pin ftsbga devices have been discontinued. figure 84. data: f_mc_wififo_full, mc_wdfifo_full clock: f_mc_wclk figure 85. data: f_mc_rififo_full, mc_rdfifo_empty clock: f_mc_rclk d 3.5/0.5 ns 1.5/0.5 ns d 1.36 / 0.38 ns fpga embedded core c 1.7/ 0.73 ns q total prop = 2.7 / 1.12 ns delay delay note: delays represent average max/min values, not absolute values actual delay values are used by isplever clock buffer delay relative to data d 3.5/0.5 ns 1.5/0.5 ns d 0.92 / 0.32 ns fpga embedded core c 1.93/ 0.84 ns q total prop = 3.0 / 1.3 ns delay delay note: delays represent average max/min values, not absolute values actual delay values are used by isplever clock buffer delay relative to data lattice semiconductor orca orspi4 data sheet 147 1036-pin ftsbga devices have been discontinued. software software for con?uration there are two ways to write to the orspi4 memory map either via mpi (microprocessor interface) or via umi (user master interface) to the fpga logic. both the interfaces use the system bus to perform the transactions with the registers. the mpi is provided to talk to any power pc microprocessor whereas umi is used for any customer- de?ed interface and interfaces extremely well with orcastra to graphically change and monitor the register map. the registers are divided into different domains, the details of which can be found in the technical note tn1017. orspi4 device core registers can be accessed by addressing the 30000 onwards domain. since there are four different macros inside the orspi4 core, all these macros have been assigned their individual sub domains. table 43. address allocation - register elements orspi4 start-up sequence spi4 link start-up protocol immediately after reset, and before the link synchronization, the spi4 link must initialize to a known interface proto- col. this section describes the initialization protocol for a generic spi4 link. the actual start-up procedure with the appropriate software register settings is described in the next section. figure 86 shows the spi4 link reference dia- gram that is referenced in the descriptions below. where appropriate, the corresponding orspi4 software register settings are also described as relevant to this start-up protocol. a reset can be either hard or soft, but is assumed that the entire spi4 link is being reset. immediately after the reset signal is deasserted and before the link synchronization, the following actions/conditions must occur/exist. figure 86. spi4 link functional block diagram 1. the receive data fifos are emptied (rx_d_b) address (0x) description 309xx spia addresses 30axx spib addresses 308xx serdes addresses 30bxx qdr mem controller addresses and some shared by spia and spib device a device b tx_d_a rx_d_b rx_s_b tx_s_a dip2 = ?k dip4 = ?k lattice semiconductor orca orspi4 data sheet 148 1036-pin ftsbga devices have been discontinued. 2. any outstanding credits are cleared in the transmit data path (tx_d_a) this is done by presetting all the credit values in the tx credit memory to 10'h000. this is done by ?st selecting the tx credit memory by writing a ? to tx_cred_mem_sel (address 30917 in spia and 30a17 in spib) and then writing to address range 31000-310ff that correspond to locations 0 - 255 in the tx credit memory. additionally, the stat ?lds for all ports must be disabled to 2'b11. this can be done by ?st selecting the tx status memory by writing a ? to tx_stat_mem_sel (address 30917 in spia and 30a17 in spib) and then writing to address range 31000 - 310ff that correspond to locations 0 - 255 in the tx status memory. 3. the data transmitter (tx_d_a as shown in figure 86) sends continuous training patterns until it receives valid fifo status on tx_s_a. a signal from the status block needs to be sent to the data block to indicate this. the transmit pdm polling is disabled at this point. 4. the receive data interface rx_d_b ignores all incoming data until it has observed the training pattern and acquired synchronization. this can be observed by polling the rx_dskw_done_sts and rx_dskw_err_sts interruptible status bits (address 3091c in spia and 30a1c in spib). this is described in detail in the next section. as long as the receiver is not deskewed (or synchronization is not complete), rx_s_b will continue to send framing pattern 2?11 on the spi4 status link. 5. rx_d_b asserts dip-4 = ?k which is indicated by a ? on the rx_algn_off_sts interruptible status bit (address 3091c in spia and 30a1c in spib). this bit is set to ? if the number of consecutive dip-4 errors exceeds the programmed threshold. this threshold is programmed by writing to rx_dip4_err_th control register bits (address 30910 in spia and 30a10 in spib). 6. after the receiver has declared link synchronization and a calendar has been provisioned, the receive status channel rx_s_b begins sending valid fifo status for each enabled port contained in the calendar. valid sta- tus is frame-based with dip-2 code words as part of the protocol. calendar is declared as ?rovisioned when rx_cal_len_main (or rx_cal_len_shd if shadow calendar is being used) has a value > 0. it is recom- mended to con?ure the calendar table and write the rx_cal_len_main last. 7. after the transmitter status channel tx_s_a receives a con?urable number of consecutive valid dip-2 code words, it begins transmitting data bursts of the enabled ports within the con?ured calendar. the dip-2 error threshold can be programmed by writing to tx_dip2_err_th (address 30944 in spia and 30a44 in spib). at this point the end-to-end link is established and valid data/status is being transferred across the spi4 link. there may be cases where the transmitter in device ? (tx_d_a) is active, but the receiver in device ? (rx_d_b) is in reset condition. in this situation, after the receive reset signal has been deasserted, the link fol- lows the procedure de?ed above from step 4. when the receiver is in a reset condition, the rx_s_b block will be sending the ? 1" framing pattern to the transmit status channel interface (tx_s_a). the transmitter will follow the procedure prescribed above as well. there are also cases where the data path transmitter in device ? (tx_d_a) is in a reset condition, and the receiver in device ? (rx_d_b) is active. in this situation, after the transmit reset signal is deasserted, the link follows the procedure de?ed above from step 2. when the transmitter is in a reset condition, the rx_d_b block will not be receiving valid dip-4 values. the rx_d_b block removes the dip-4 = ?k signal and the rx_s_b block begins to send continuous ? 1" framing pattern to the transmit status channel interface (tx_s_a). spia or spib start-up sequence after the device is powered up, it resets itself with a power-up reset, designed to trigger itself at power up. the ?st thing required by the orspi4, is to perform baseline process followed by training if dynamic alignment is chosen (spi4_low_speed_data_sel = ??. this is required by the spia and spib high-speed receivers for internal lattice semiconductor orca orspi4 data sheet 149 1036-pin ftsbga devices have been discontinued. alignment. dynamic alignment may also be required during normal transmission and reception of spi4 data because process, voltage and temperature variations can alter the alignment. the procedure is as follows (only shown for spia) enable the interrupts related to the high-speed receive interface block by writing ff to 30913. this would enable the status update on the register 3091c. it is also recommended to enable other interrupts as well. for example registers 30912 and 30914 so that the corresponding statuses can be monitored. set register 30910 to 0x71 this would set the dip4 error threshold to 7 and will enable baseline for spia to per- form ?rspi4 baseline procedure. dip4 error threshold is set to 7 for experimental reasons only, most of the applications engineers would want to set it to 1 to ?g any single dip4 error. soft-reset the spia core by writing 0x02 to 30b20 and then clearing this bit. this can also be achieved by pulsing the s4a_fpga_reset fpga/core interface pin. please note that every time the orspi4 core is soft-reset the txpdm contents are erased whereas the contents of rxpdm, rxcal and txcal remain intact. software engi- neers would want to put a state machine in the api to reprogram the txpdm once the soft reset is pulsed. soft reset may be required to pulse if because of any reason orspi4 loses its synchronization with another device. in that case ?rspi4 baseline procedure needs to be performed again by pulsing the soft reset. read the 3091c register - it should read 0x53 bit 0 = 0 indicates that the rdi pll has locked to the refclka. if the rdclk (spi4 receive clock) is present then the pll will lock to the rdclk. bit 1 = 1 indicates that the baseline has been done bit 2 = 0 indicates that there are no baseline errors bit 3 = 1 indicates that receive de-skew has been achieved. this bit will stay high if the enable training is not set in the register 30910, it will also be set once the training has been done. bit 4 = 0 indicates that there are no receive de-skew errors, these errors will only show up if the training has been enabled and de-skewing is not successful. bit 5 = 0 indicates that training is not detected bit 6 = 1 indicates that byte-lanes' alignment is off, this bit is also relevant if the training is enabled and bytes are not being aligned properly. bit 7 = 1 indicates that the tx status is showing lof, because the tx_cal_m_main and tx_cal_len_main do not match the rx_cal_m_main and rx_cal_len_main respectively. enable internal loopback by writing 0x08 to 30915. this is only required if there is no other spi4 device talking to orspi4. external loopback can also be performed in which case this register bit should not be set. program the tx_data_max_t and tx_alpha values in the registers 30935, 30936, 30937, 30940, 30941 and 30942. setting a non-zero value to these registers will automatically cause the transmit block to initiate the spi4 training sequence. program the rx_fifo_threshold_h (30911) and tx_fifo_threshold_h (30945) values to 0x78 and 0x17 respectively. these are watermarks for internal asynchronous fifos. these are the recommended values. if minburst mode is desired then tx_fifo_threshold_h needs to be set appropriately. refer to min- burst mode section of the data sheet. keep baseline enabled and, enable training by writing 0x73 to 30910. read the 3091c register and it should read 0x55 bit 0 = 0 indicates that the receive pll has locked to refclka or rdclk. bit 1 = 1 indicates that the baseline has been done bit 2 = 0 indicates that there are no baseline errors bit 3 = 1 indicates that rdi de-skew has been achieved bit 4 = 0 indicates that there are no rdi de-skew errors bit 5 = 1 indicates that training is detected. bit 6 = 0 indicates that byte-lanes' alignment is not off. bit 7 = 1 indicates that the tx status is showing lof, because the tx_cal_m_main and lattice semiconductor orca orspi4 data sheet 150 1036-pin ftsbga devices have been discontinued. tx_cal_len_main do not match the rx_cal_m_main and rx_cal_len_main respectively. it is recommended that the training be kept enabled at all times so the dynamic alignment is performed to com- pensate for process, voltage and temperature variations. program the tx_cal_m_main equal to rx_cal_m_main and tx_cal_len_main equal to rx_cal_len_main and then the register 3091c should read 54. read register 3091d twice, the ?st value read could indicate dip4 and dip2 errors, if clears to 00 after the sec- ond read then there are no errors. the errors during the ?st read indicate that the errors existed before the train- ing was performed. read the register 3090a to read the dip4 error count. this register will keep counting if the bit 5 of 3091d is set, otherwise this register will show 00. read the register 3090b to read the dip2 error count. this register will keep counting if the bit 6 of 3091d is set, otherwise this register will show 00. after the above con?uration is completed, the device is not yet ready to transmit and receive data. the user still has to provision the calendars and the port descriptor memories for appropriate bandwidth. this is an indirect addressing mechanism where a single bit in register 30917 selects which memory space needs to be addressed. once one of the bit is selected then the user can write to 31000 to 31fff address space. the following example shows how to program tx pdm, rx pdm, tx calendar and rx calendar. four ports (0, 1, 2 and 3) of spi4 data with equal bandwidth. no dpram partitions (virtual fifos). write 20 hex to 30917 to select the rx calendar indirect addressing next program the rx calendar memory through the following writes: write 00 to the 31000 location. write 01 to the 31001 location. write 02 to the 31002 location. write 03 to the 31003 location. write 10 hex to register 30917 to select the rx pdm indirect addressing. since there are no partitions for the dprams, only the bits which correspond to the bank_id of the dprams will be written. bits that correspond to the partition_id of the dprams are written to ?00? write 00 hex to the 31000 location which means that data will read from the dpram0 for port 0. write 08 hex to the 31001 location which means that data will be read from the dpram1 for port 1. write 10 hex to the 31002 location which means that data will be read from the dpram2 for port 2. write 18 hex to the 31003 location which means that data will be read from the dpram3 for port 3. write 08 hex to 30917 to select the tx calendar indirect addressing write 00 to the 31000 location. write 01 to the 31001 location. write 02 to the 31002 location. write 03 to the 31003 location. write 04 hex to 30917 to select the tx pdm indirect addressing. tx pdm has a total of 6 ?lds to be written and they are divided into 3 bytes. these three bytes correspond to a single memory location for tx pdm, which has a total of 256 locations. write the port id 00 hex to 31000 corresponding to port 0. write 0f hex to 31001 (000 to partition id ?ld and 1111 to burst_val ?ld). write 0c hex to 31002 which implies: mb_en bit is set to ? which means that max-burst1 and max-burst2 both will be supported, otherwise only max-burst1 will be used. m bit is set to ? which means the port id ?ld programmed in the tx pdm is propagated to the fpga on the lattice semiconductor orca orspi4 data sheet 151 1036-pin ftsbga devices have been discontinued. spia_txk_port_id (k=32, 64, 128) signal. if m bit is not set then the port id programmed in the tx calendar will be broadcast to the fpga. dpram bank_id ?ld is set to ?0? address location 31003 is not used. write 01 hex to 31004 corresponding to port 1. write 0f hex to 31005 (000 to partition id ?ld and 1111 to burst_val ?ld). write 0d hex to 31006 (mb_en bit is set to ?? m bit is set to ? and dpram bank_id ?ld is set to ?1?. address location 31007 is not used. write 02 hex to 31008 corresponding to port 2. write 0f hex to 31009 (000 to partition id ?ld and 1111 to burst_val ?ld). write 0e hex to 3100a (mb_en bit is set to ?? m bit is set to ? and dpram bank_id ?ld is set to ?0?. address location 3100b is not used. write 03 hex to 3100c corresponding to port 3. write 0f hex to 3100d (000 to partition id ?ld and 1111 to burst_val ?ld). write 0f hex to 3100e (mb_en bit is set to ?? m bit is set to ? and dpram bank_id ?ld is set to ?0?. address location 3100f is not used. this concludes the con?uration of the orspi4 spia core in the dynamic mode. in low speed static mode (bit 2 of register 30915 selected) and in low speed quarter rate static mode (bit 0 of register 30915 selected), the baseline procedure and the training procedure is not required. this means that the high speed pll is bypassed and therefore the bit 0 of register 30910 will always be high. in static mode this is normal and should be ignored. in fact the only relevant bits in register 30910 are bits 6 and 7. if these bits are not high then that means orspi4 has hand-shaken with another device properly. delay-taps in static mode after all the con?uration procedure is performed, there is a possibility of orspi4 experiencing dip-4 errors and rx alignment status ?g being high. this can be tackled using two fpga/core interface signals called spi_datm_a and spi_dlytap_a [2:0]. with spi_datm_a set to high, spi_dlytap_a[2:0] should be varied from 0 to 6 to adjust the rx data with respect to rdclk to get a valid data eye. this would help getting rid of the dip4 errors and the rx alignment status ?g. this procedure is also a function of how the board designer has laid out the 16 rx_data lanes. if all the lengths are grossly mismatched then this mechanism may not work, so it is imper- ative to design the board keeping the lengths of the rx_data as close as possible. serdes start-up sequence the following sequence is required by the serdes. for information required for simulation that may be different than this sequence, see the orspi4 design kit. 1. initiate a hardware reset by making resetn low. keep this low during fpga con?uration of the device. the device will be ready for operation 3 ms after the low to high transition of resetn. 2. con?ure the following serdes internal and external registers. note that after device initialization, all alarm and status bits should be read once to clear them. a subsequent read will provide the valid state. set the fol- lowing bits in register 30800: bits lckrefn_[a:d] to ?? which implies lock to data. bits enbysync_[a:d] to ? which enables dynamic alignment to comma. set the following bits in register 30801: bits loopenb_[a:d] to ? if high-speed serial loopback is desired. set the following bits in registers 30002, 30012, 30022, 30032: txhr set to ? if tx half-rate is desired. lattice semiconductor orca orspi4 data sheet 152 1036-pin ftsbga devices have been discontinued. 8b10bt set to ? set the following bits in registers 30003, 30013, 30023, 30033: rxhr set to ? if rx half-rate is desired. 8b10br set to ?? linksm set to ? if the fibre channel state machine is desired. assert gswrst bit by writing two ??s. deassert gswrst bit by writing two ??. wait 3ms. if higher speed serial loopback has been selected, the receive plls will use this time to lock to the new serial data. monitor the following alarm bits in registers 30000, 30010, 30020, 30030: lki, pll lock indicator. ? indicates that pll has achieved lock. 3. if 8b/10b mode is enabled, enable link synchronization by periodically sending the following sequence three times: k28.5 d21.4 d21.5 d21.5 or any other idle ordered set (starting with a /comma/) in fc mode. /comma/ characters for the xaui state machine and /a/ characters for word and channel alignment in xaui resets global resets global resets affect all blocks in the orspi4 embedded asic core (eac) section (spia, spib, mc, mpi, and serdes. a global reset can be caused by one the following: power-up reset, bitstream download without a partial recon?uration enabled, hardware reset, or fpga global set reset (gsr). power-up reset the power-up reset process begins when the power supply voltage ramps up to approximately 80% of the nominal value of 1.5 v. following this event, the device will be ready for normal operation after 3 ms. for more information on power-up reset, please refer to the orca series 4 fpga data sheet at www.latticesemi.com. bitstream download (done=0) during bitstream download, the fpga done signal remains low until the part is fully con?ured during this time, all orspi4 eac blocks remain in reset. during partial recon?uration, an fpga register bit can be set to prevent a reset of the eac while done=0. for more information on bitstream con?uration, please refer to the orca series 4 fpga data sheet at www.latticesemi.com. hardware reset (resetn) a hardware reset is initiated by making the resetn low for at least two microprocessor clock cycles. the device will be ready for operation 3 ms after the low to high transition of the resetn. this reset function affects all eac blocks. fpga global set reset (gsr) the fpga global set reset signal (gsr) can be made to reset the spia, spib and serdes blocks of the orspi4 core. this can be done during the orspi4 module/ip generation phase of the orspi4 core in isplever . during this phase, the ?isable gsr from resetting data path in fpsc core check button is left unchecked to enable gsr to reset these blocks. for more information on gsr, please refer to the orca series 4 fpga data sheet at www .latticesemi.com . spia-only resets the spia block can be individually reset though software reset-via the microprocessor interface, or using an fpga interface signal. lattice semiconductor orca orspi4 data sheet 153 1036-pin ftsbga devices have been discontinued. software reset (soft_reset_s4a) a register bit used to reset the spia is soft_reset_ s4a (30b20, bit 6). this bit, when set to ?? disables the spia block. fpga interface reset (fpga_reset_s4a) fpga_reset_s4a performs the same function as soft_reset_ s4a. the difference is that it is an fpga interface signal instead of a con?uration register bit. spib-only resets the spib block can be individually reset though software reset-via the microprocessor interface, or using an fpga interface signal. software reset (soft_reset_s4b) a register bit used to reset the spib is soft_reset_ s4b (30b20, bit 7). this bit, when set to ?? disables the spib block. fpga interface reset (fpga_reset_s4b) fpga_reset_s4b performs the same function as soft_reset_ s4b. the difference is that it is an fpga interface signal instead of a con?uration register bit. mc-only resets the memory controller (mc) block can be individually reset though software reset-via the microprocessor inter- face, or using an fpga interface signal. software reset (soft_reset_mc) a register bit used to reset the mc is soft_reset_ mc (30b20, bit 5). this bit, when set to ?? disables the mc block. fpga interface reset (fpga_reset_mc) fpga_reset_mc performs the same function as soft_reset_ mc. the difference is that it is an fpga inter- face signal instead of a con?uration register bit. serdes-only resets the serdes block can be individually reset though software reset-via the microprocessor interface, or using fpga interface signals. software reset (swrst and hard_reset_fc) using the software reset option via the microprocessor interface, each channel can be individually reset by setting swrstx (bit 2) to a logic ? in the channel con?uration register (30004,30014,30024,30034)). the device will be ready 3 ms after the swrstx bit is de-asserted. similarly, all four channels per quad serdes can be reset by set- ting the global reset bit gswrst (30005, bit 2). the device will be ready for normal operation 3 ms after the gswrst bit is de-asserted. note that the software reset option resets only serdes internal registers and counters. the microprocessor registers are not affected. it should also be noted that the embedded block couldn't be accessed until after fpga con?uration is complete. also note that the swrstx and gswrst are active when the corresponding memory map register bit is set high. another register bit used to reset the serdes is hard_reset_fc (30b20, bit 4). this bit, when active, disables the serdes and prevents any access to its internal microprocessor registers (300xx range). fpga interface reset signals (sys_rst_n and fpga_reset_fc) fpga_reset_fc performs the same function as hard_reset_fc. the difference is that it is an fpga inter- face signal instead of a con?uration register bit. sys_rst_n is a synchronous active low reset fpga interface signal. this signal, when active, resets the read side of the multi-channel alignment fifos. lattice semiconductor orca orspi4 data sheet 154 1036-pin ftsbga devices have been discontinued. the following table describes the different methods of resetting various parts of the eac. it lists the logic values set on the fpga interface and the primary asb pins. table 44. orspi4 reset 1. please refer to the orca series 4 fpga data sheet at www .latticesemi.com . i/o tri-state functions the eac i/os can be tri-stated using one of the three signals below. ts_all this is an fpga signal that globally tri-states all eac ios in addition to the fpga ios. for more information on ts_all, please refer to the orca series 4 fpga data sheet at http://www .latticesemi.com . tristn this is an orspi4 eac active low io that globally tri-states all eac ios. power-up in addition to its reset function, power-up also puts the orspi4 fpsc io in tri-state until the chip is fully pow- ered up. power down when set low, the orspi4 fpsc ?dn powers down the following: all plls in the spia, spib, memory controller and serdes lvds and hstl buffers on the eac section of the orspi4 spia, spib, and serdes logic signal name reset type orspi4 core affected mpi spia spib m_ctrl serdes pwrupres = 1 fpga signal 1 done = 0 fpga i/o 1 resetn = 0 eac io gsrn = 0 and gsrn_disable = 0 fpga signal fpga_reset_s4a = 1 interface signal soft_reset_s4a = 1 software register bit fpga_reset_s4b = 1 interface signal soft_reset_s4b = 1 software register bit fpga_reset_mc = 1 interface signal soft_reset_mc = 1 software register bit fpga_reset_fc = 1 interface signal hard_reset_fc = 1 software register bit sys_rst_n (channel alignment fifo reset) interface signal lattice semiconductor orca orspi4 data sheet 155 1036-pin ftsbga devices have been discontinued. orspi4 memory map the orspi4 device features a variety of programming options which include all the oif-spi-4.2.0 speci?d con?- urable parameters. the base addresses for each functional block in the orspi4 device is shown in figure 87 and table 45. the spia and spib receive cores contain ram blocks that are con?ured through writes to the address range 0x31000 - 0x317ff. prior to con?uring any of these memories, the user has to select one of the memories by writ- ing into the appropriate memory select bit in address 0x30917 (spia) and 0x30a17 (spib). all interrupts on orspi4 are maskable and edge generated. each interrupt source has a corresponding status latch bit that can be viewed as software status register bits. at the end of a status register read, both the status and edge-triggered interrupt register will be cleared. if the active interrupt condition still persists after the status register read, the status register will continue to show this condition but the edge-triggered interrupt register will remain clear not causing another interrupt. every interrupt or status register bit has an interrupt enable bit that must be set to ? to generate the associated interrupt or read the status. each interrupt enable for the dprams in spia and spi4 blocks controls or enables eight interrupt sources. these enable registers are at register address 30912, 30943, (spia) 30a12, and 30a43 (spib). these 32 bits enable/disable 256 interrupts. all other interrupt enables are unique to an interrupt source. to make the interrupt structure user-friendly, two special top-level interrupt registers are provided. each of the bits in these top-level interrupt registers point to speci? functional blocks that caused an interrupt. the user can poll these top-level interrupt registers to check which block has caused an interrupt and then poll the relevant lower- level interrupts corresponding to a block. each of the bits in the top-level interrupt status register 30b29 shown in table 46 point to a speci? functional block in the orspi4 device. each of the bits in the spia or spib dpram top- level interrupt status register 30b2a is the collective or of its associated lower-level interrupts. figure 87. spi4 core programming addresses in orspi4 fpga sys_bus slave_if control & status registers to control serdes channels control & status registers to control spia control & status registers to control spib global configuration memories mem_if 308xx 309xx 30axx 30bxx core_if spi4_if spi4_if comm_if 3xxxx hex address lattice semiconductor orca orspi4 data sheet 156 1036-pin ftsbga devices have been discontinued. table 45. orspi4 memory space table 46. top-level interrupt status register 30b29 table 47 details the memory map for the fpsc portion of the orspi4 device. addresses for the control registers for the fpga portion of the device are detailed in the orca series 4 datasheet. this table shows the databus oriented for the ppc interface. db0 is the msb, while db7 is the lsb. if the user master interface is used to perform operations to the asic core then the databus must be used in the opposite notation, where db7 is the msb and db0 is the lsb. address (hex) description 3000x channel a in serdes, internal registers 3001x channel b in serdes, internal registers 3002x channel c in serdes, internal registers 3003x channel d in serdes, internal registers 308xx channel registers outside the serdes 3090x - 3092x spi4 core a control registers 30930 - 3094x spi4 core a status registers 30950 - 3097x spi4 core b control registers 30980 - 3099x spi4 core b status registers 31000 - 317ff spi4 core a/b con?urable ram address space 30100 - 3010f memory controller registers bit interrupt source associated registers 0 serdes 3000, 3010, 3020, 3030 1 memory controller 30b09 2 memory controller 30b08 3 dpram spia (3090c-3090f, 30918-3091b, 30928-3092f) spib (30a0c-3090f, 30a18-30a1b, 30a28-30a2f) 4 spi_b_2 30a1c 5 spi_b_1 30a1d 6 spi_a_2 3091c 7 spi_a_1 3091d table 47. memory map (0x) abso- lute address bit name reset value (0x) description serdes alarm registers (read only), x = [a, ...,d] 30000 30010 30020 30030 [0] reserved [1] lki_x 00 receive pll lock indication, channel x. lki_x = ? indicates the receive pll is locked. [2:7] reserved lattice semiconductor orca orspi4 data sheet 157 1036-pin ftsbga devices have been discontinued. serdes alarm mask registers (read/write), x = [a, ...,d] 30001 30011 30021 30031 [0] reserved ff reserved. must be set to ?? set to ? on device reset. [1] mlki_x mask receive pll lock indication, channel x. [2:7] reserved serdes common transmit and receive channel con?uration registers (read/write), x = [a, ...,d] 30002 30012 30022 30032 [0] txhr_x 00 transmit half rate selection bit, channel x. when txhr_x = ?? hdout_x's baud rate = (refclk*10) and tck78 =(refclk/4); when txhr_x=0, hdout_x's baud rate = (refclk*20) and tck78=(refclk[a:b]/2). txhr_x = 0 on device reset. [1] pwrdnt_x transmit powerdown control bit, channel x. when pwrdnt_x = ?? sec- tions of the transmit hardware are powered down to conserve power. pwrdnt_x = 0 on device reset. [2] pe0_x transmit preemphasis selection bit 0, channel x. pe0_x and pe1_x select one of three preemphasis settings for the transmit section. peo_x=pe1_x = 0, preemphasis is 0% peo_x=1, pe1_x = 0 or peo_x=0, pe1_x = 1, preemphasis is 12.5% peo_x=pe1_x = 1, preemphasis is 25%. peo_x=pe1_x = 0 on device reset. [3] pe1_x [4] hamp_x transmit half amplitude selection bit, channel x. when hamp_x = ?? the transmit output buffer voltage swing is limited to half its normal amplitude. otherwise, the transmit output buffer maintains its full voltage swing. hamp_x = 0 on device reset. [5] reserved reserved. must be set to 0 set to ? on device reset. [6] reserved [7] 8b10bt_x transmit 8b/10b encoder enable bit, channel x. when 8b10bt_x = ?? the 8b/10b encoder in the transmit path is enabled. otherwise, the data is passed unencoded. 8b10bt_x = ? on device reset. 30003 30013 30023 30033 [0] rxhr_x 20 receive half rate selection bit, channel x. when rxhr_x =?? hdin_x's baud rate = (refclk*10) and rck78=(refclk/4); when rxhr_x= ?? hdin_x's baud rate = (ref- clk*20) and rck78=(refclk/2). rxhr_x = ? on device reset. [1] pwrdnr_x receiver power down control bit, channel x. when pwrdnr_x = 1, sec- tions of the receive hardware are powered down to conserve power. pwrdnr_x = ? on device reset. [2] reserved reserved. must be set to ?? set to ? on device reset. [3] 8b10br_x receive 8b/10b decoder enable bit, channel x. when 8b10br = ?? the 8b/10b decoder in the receive path is enabled. otherwise, the data is passed undeocded. 8b10br_x = ? on device reset. [4] linksm_x link state machine enable bit, channel x. when linksm_x = ?? the receiver fiber channel link state machine is enabled. otherwise, the fibre channel link state machine is disabled. note: linksm_x is ignored when xaui_mode_x= ?? linksm_x = ? on device reset. [5:7] reserved table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 158 1036-pin ftsbga devices have been discontinued. serdes common transmit and receive channel con?uration registers (read/write), x = [a, ...,d] 30004 30014 30024 30034 [0] reserved 40 reserved. must be set to ? set to ? on device reset. [1] mask_x transmit and receive alarm mask bit, channel x. when mask_x = ?? the transmit and receive alarms of a channel are prevented from generating an interrupt (i.e., they are masked or disabled). the mask_x bit overrides the individual alarm mask bits in the alarm mask registers. mask_x = ? on device reset. [2] swrst_x transmit and receive software reset bit, channel x. when swrst_x = ?? this bit provides the same function as the hardware reset, except that all con?uration register settings are unaltered. this is not a self-clearing bit. once set, this bit must be manually set and cleared. swrst_x = ? on device reset. [3:6] reserved [7] testen_x transmit and receive test enable bit, channel x. when testen_x = ?? the transmit and receive sections are placed in test mode. the test- mode[4:0] bits in the global control registers specify the particular test, and must also be set. note: when the global test enable bit gtesten = ?? the individual chan- nel test enable bits are used to selectively place a channel in test or normal mode. when gtesten = ?? all channels are set to test mode regardless of their testen setting testen_x = ? on device reset. serdes global control registers (read/write) acts on all four channels in serdes quad a or serdes quad b. 30005 [0] reserved 44 reserved set to ? on device reset. [1] gmask global mask. when gmask = ?? the transmit and receive alarms of all channel in the serdes quad are prevented from generating an interrupt (i.e., they are masked or disabled). the gmask bit overrides the individual mask_x bits. gmask = ? on device reset. [2] gswrst software reset bit. the gswrst bit provides the same function as the hardware reset for the transmit and receive sections of all four channels, except that the device con?uration settings are not affected when gswrst is asserted. this is not a self-clearing bit. once set, this bit must be manually set and cleared. the gswrst bit overrides the individual swrst_x bits. gswrst = ? on device reset. [3] gpwrdnt powerdown transmit function. when gpwrdnt = ?? sections of the transmit hardware for all four channels of are powered down to conserve power. the gpwrdnt bit overrides the individual pwrdnt_x bits. gpwrdnt= ? on device reset. [4] gpwrdnr powerdown receive function. when gpwrdnr = ?? sections of the receive hardware for all four channels are powered down to conserve power. the gpwrdnr bit overrides the individual pwrdnr_x bits. gpwrdnr = ? on device reset. [5] reserved reserved, ? on device reset. [6] reserved [7] gtesten test enable control. when gtesten = ?? the transmit and receive sec- tions of all four channels are placed in test mode. the gtesten bit over- rides the individual testen_x bits. gtesten = ? on device reset. 30006 [0:4] testmode 00 testmode - see test mode section for settings [5:7] reserved table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 159 1036-pin ftsbga devices have been discontinued. control registers (read/write), x = [a, ...,d] 30800 [0]a [1]b [2]c [3]d enbysync[a:d] 00 enbysync[a:d] = ? enables receiver byte synchronization for channel x. enbysync[a:d] = ? on device reset. [4]a [5]b [6]c [7][d] lckrefn[a:d] lckrefn[a:d]= ? locks the receiver pll to ref reference clock for chan- nel x. lckrefn[a:d]= ? = locks the receiver to data for channel x. note: when lckrefn[a:d] = ?? the corresponding lki_x bit is also zero. lckrefn[a:d]= ? on device reset. 30801 [0]a [1]b [2]c [3]d loopenb[a:d] enable loopback mode for channel x. when loopen[a:d]= ?? the trans- mitter high-speed output is looped back to the receiver high-speed input. this mode is similar to high-speed loopback mode enabled by test- mode[a:d] except that loopen[a:d] disables the high-speed serial out- put. loopen[a:d]= ? on device reset. [4]a [5]b [6]c [7]d nowdalign[a:d] word align disable bit. when nowdalign[a:d]= ?? receiver word align- ment is disabled for channel x. nowdalign[a:d]= ? on device reset. 30810 [0]a [1]b [2]c [3]d dowdalign[a:d] 00 word realign bit. when dowdalign[a:d] transitions from ? to ?? the receiver realigns on the next comma character for channel x. dowdalign[a:d]= ? on device reset. [4]a [5]b [6]c [7]d fmpu_str_en[a:d] enable multi-channel alignment for channel x. when fmpu_str_en[a:d]= ?? the corresponding channel participates in multi- channel alignment. fmpu_str_en[a:d]= ? on device reset. 30811 [0:1]a [2:3]b [4:5]c [6:7]d fmpu_synmode[a: d][0:1] 00 sync mode for x 00 = no channel alignment 10 = twin channel alignment 01 = quad channel alignment 30820 [0]a [1]b [2]c [3]d fmpu_resync1[a: d] 00 resync a single channel. when fmpu_resync1[a:d] transitions from ? to ?? the corresponding channel is resynchronized (the write and read pointers are reset). fmpu_resync1[a:d]=? on device reset. [4]a & b [5]c &d fmpu_resync2[1: 2] 00 resync a pair of channels. when fmpu_resync2[1:2] transitions from a ? to a ?? the corresponding channel pair is resynchronized. ffmpu_resync2[1:2]= ? on device reset. [6] fmpu_resync4[1: 2] 00 resync a four-channel group. when fmpu_resync4 transitions from a ? to a ?? the corresponding four-channel group is resynchronized. fmpu_resync4= ? on device reset. [7] xaui_mode 00 controls use of xaui link state machine in place of fibre-channel state machine. when xaui_mode= ?? all four channels in the serdes quad enable their xaui link state machines. (linksm_x bits are ignored). xaui_mode= ? on device reset. table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 160 1036-pin ftsbga devices have been discontinued. 30821 [0] nochalgn bypass channel alignment. nochalgn =1 causes bypassing of multi- channel alignment fifos for the corresponding serdes quad. nochalgn = ? on device reset. [1:3] reserved [4:5] rcksel[0:1] 00 source for rck78 (00=a, 10=b, 01=c, 11=d) [6:7] tcksel[0:1] 00 source for tck78 (00=a, 10=b, 01=c, 11=d) 30830 [0:3] reserved [4] schar_ena 00 set this to 1 to enable characterization mode for the serdes. character- ization mode also requires inputs testmd[1:0]n=00, and fpga interface pin, enable_spi4_b = ?? the outputs for the serdes can be observed at the following ports: tbc311 pmid20 cv pmid21 bytsync pmid22 wdsync pmid23 rbco pmid24 rbc1 pmid25 ldout9 pmid26 ldout8 pmid 27 ldout7 pmid28 ldout6 pmid29 ldout5 pmid30 ldout4 pmid31 ldout3 pmid32 ldout2 pmid33 ldout1 pmid34 ldout0 pmid35 [5] schar_txsel set this to 1 to enable driving of low speed tx ports of the serdes during characterization mode. the inputs used during this mode are: tbc pmia15 ldin9 pmia14 ldin8 pmia13 ldin7 pmia11 ldin6 pmia9 ldin5 pmai8 ldin4 pmia7 ldin3 pmia6 ldin2 pmia5 ldin1 pmia4 ldin0 pmia2 [6:7] schar_chan selects the channel to observe and control during serdes characterization mode: 00 = a 01 = b 10 = c 11 = d status registers (read only), x = [a, ...,d] 30804 [0:1]a [2:3]b [4:5]c [6:7]d xauistat[a:d][0:1] 00 xaui status register. status of xaui link state machine for channel x 00?o synchronization. 01?o comma (see xaui state machine) and at least 1 cell value detected 10?ynchronization done. 11?ot used. xauistat_x[0:1] = 00 on device reset. table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 161 1036-pin ftsbga devices have been discontinued. 30805 [0]a [1]b [2]c [3]d demuxwas[a:d] 00 status of word alignment. when demux_was[a:d] = ?? word alignment is achieved for channel x. demux_was[a:d]= ? on device reset. [4]a [5]b [6]c [7]d ch248_sync[a:d] status of channel alignment. when ch248_sync[a:d] = ?? multi-channel alignment is achieved for channel x. ch248_sync[a:d]= ? on device reset. 30814 [0:2] reserved [3]a&b [4]c& d sync2[1:2]oosl multi-channel out-of-sync status. when sync2[1:2] oos= ?? dual-chan- nel synchronization has failed. sync2[1:2] oos on device reset. [5] sync4oos multi-channel out-of-sync status. when sync4_oos= ?? quad-channel synchronization has failed. sync4_oos= ? on device reset. [6:7] reserved spi4 core rx control registers (read and write) 30900 a 30a00 b [0:7] rx_cal_m_main 00 number of times calendar sequence is repeated between insertions of fram- ing pattern (rx spi4, main) 30901 a 30a01 b [0:5] reserved [6:7] rx_cal_len_main 00 length of calendar sequence on the rx status frame (spi4, main) this is the most signi?ant 2 bits of 10 total. 30902 a 30a02 b [0:7] rx_cal_len_main 00 length of calendar sequence on the rx status frame (spi4, main). this is the least signi?ant 8 bits of 10 total 30903 a 30a03 b [0:7] rx_cal_m_shd 00 number of times shadow calendar sequence is repeated between insertions of framing pattern for the rx side of spi4. 30904 a 30a04 b [0:5] reserved [6:7] rx_cal_len_shd 00 shadow calendar length for the rx status frame of spi4. upper 2 bits. 30905 a 30a05 [0:7] rx_cal_len_shd 00 shadow calendar length for the rx status frame of spi4. lower 8 bits. 30906 a 30a06 b [0:1] rx_dpram_0_num fifo 00 number of virtual fifos in rx dpram bank 0 00 = 1 fifo 01 = 2 fifos 10 = 4 fifos 11 = 8 fifos [2:3] rx_dpram_1_num fifo number of virtual fifos in rx dpram bank 1 [4:5] rx_dpram_2_num fifo number of virtual fifos in rx dpram bank 2 [6:7] rx_dpram_3_num fifo number of virtual fifos in rx dpram bank 3 table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 162 1036-pin ftsbga devices have been discontinued. 30907 a 30a07 b [0:1] rx_dpram_0_agg r_mode 00 rx bank 0 aggregation mode 00 = 32 bit data 01 = 64 bit data 10 = 128 bit data 11 = not valid [2:3] rx_dpram_1_agg r_mode rx bank 1 aggregation mode [4:5] rx_dpram_2_agg r_mode rx bank 2 aggregation mode [6:7] rx_dpram_3_agg r_mode rx bank 3 aggregation mode 30910 a 30a10 b [0] reserved [1:3] rx_dip4_err_th 00 number of consecutive bad/good dip-4 code words for spi4 rx to lose/gain alignment. loss of alignment is indicated by rx_algn_off_sts [4] rx_disable_stat us causes 11 word to be sent on rx status frame. in turn causes far-end tx to cancel all credits and send a training pattern. [5] rx_mask_dip4 allows spi4 link to be used in presence of errors on data input. [6] rx_en_training enable detection of training patterns on the rx side. [7] rx_en_baseline enable rx baseline process 30911 a 30a11 b [0:7] rx_fifo_thresho ld_h 00 high watermark threshold for async fifo within rdp. 30912 a 30a12 b [0:3] rx_dpram_fifo_ overrun_int_en 00 these bits act as an enable for the status ?gs and the interrupts regarding overrun of the 4 rx dpram fifo banks. [4:7] rx_dpram_fifo_u rrun_int_en these bits act as an enable for the status ?gs and the interrupts regarding underrun of the 4 rx dpram fifo banks. 30913 a 30a13 b [0] rx_pll_lol_int_e n 00 this bit enables the status ?g and the interrupt regarding loss of lock in the spi4 core (high-speed macrocell) pll. see rx_pll_lol_sts in register 3091c[a], 3091c[b]. [1] rx_bas_done_int _en this bit enables the status ?g and the interrupt for the spi4 core when rdi completes the baselining process. baselining is the self-alignment power-up process that the macro does after it detects lock of the pll. see rx_bas_done_sts in register 3091c[a], 3091c[b]. [2] rx_bas_err_int_ en this bit enables the status ?g and the interrupt for the spi4 core when rdi fails its internal self-alignment process. see rx_bas_err_sts in register 3091c[a], 3091c[b]. [3] rx_dskw_done_i nt_en this bit enables the status ?g and the interrupt for the spi4 core when rdi completes its dynamic alignment process. see rx_dskw_done_sts in register 3091c[a], 3091c[b]. [4] rx_dskw_err_in t_en this bit enables the status ?g and the interrupt for the spi4 core when rdi fails to dynamically align. see rx_dskw_err_sts in register 3091c[a], 3091c[b]. [5] rx_trn_det_int_ en this bit enables the status ?g and the interrupt for the spi4 core when rdi detects training patterns. see rx_trn_det_sts in register 3091c[a], 3091c[b]. [6] rx_algn_off_int _en this bit enables the status ?g and the interrupt for the spi4 core loss of rx alignment due to excess consecutive dip4 errors. see rx_algn_off_sts in register 3091c[a], 3091c[b]. [7] tx_status_lof_in t_en this bit enables the status ?g and the interrupt for the spi4 core tx status from having too many consecutive dip2 errors. see tx_status_lof_sts table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 163 1036-pin ftsbga devices have been discontinued. spi4 core tx/rx control registers (read and write) 30914 a 30a14 b [0] reserved 00 [1] reserved [2] rx_illegal_ctl_i nt_en this bit enables the status ?g and the interrupt when the spi4 receives unsupported extended control words. [3:4] reserved [5] rx_dip4_int_en this bit enables the status ?g and the interrupt for the spi4 core rx detec- tion of a dip4 error. [6] tx_dip2_int_en this bit enables the status ?g and the interrupt for the spi4 core tx detec- tion of a status framing error (either dip2 or unexpected 11 pattern). [7] rx_async_fifo_o verrun_int_en this bit enables the status ?g and the interrupt for the spi4 core asynchro- nous fifo in rdp block being overrun. 30915 a 30a15 b [0] spi4_quarter_ra te 00 when set to ?? enables data rates of 100 - 200 mbps. the plls in the transmit and receive spi4 high-speed blocks are bypassed in this mode. [1] spi4_loopbk_fe this control enables far-end loopback when it is set to 1. far-end loopback sends rdat inputs back to tdat outputs, sends rdclk back to tdclk, sends tstat back to rstat outputs, and atsclk back to rsclk. [2] spi4_low_speed_ data_sel forces low speed data rates of (400-622 mbits/s). the transmit pll is still used to synthesize the spi4 transmit clock tdclk. however, the dynamic alignment block in the receive side is bypassed. no training sequences are used in low speed mode. [3] spi4_status_io_s el ? - selects lvttl i/o for spi4 status ? - selects lvds i/os for spi4 status (full-rate lvds status i/os speci?d by oif spi4.0 is not supported). [4] spi4_loopbk_hs enables loops from high-speed spi4 tdat outputs to rdat inputs and rstat to tstat status inputs just before i/o. [5] spi4_loopbk_ls enables near-end parallel loop from tdp to rdp blocks and rsp to tsp blocks bypassing the high-speed spi4 interface logic blocks. must enable spi4_loopbk_hs for this to work. [6] tx_force_dip4_e rr causes tdp to send bad parity code words. [7] rx_force_dip2_e rr causes rsp to send bad parity code words. 30916 a 30a16 b [0:2] reserved [3] min_burst_mode 00 set minimum burst mode for transmit path [4] rx_cal_sw_en inserts the calendar select word after the frame sync pattern on the receive spi4 status channel [5] rx_cal_sel 0 = selects main calendar for outgoing rx status frame (calendar select word will be ?1? 1 = selects shadow calendar (calendar select word will be ?0? [6] tx_cal_sw_en detect the calendar select word after the frame sync pattern on the transmit status [7] tx_burst_termin ation mode control for managing the transmission of bursts when the dpram partition becomes empty in the middle of a burst. 0 =continue to try to access dpram for the remainder of burst. 1 = abort the burst. table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 164 1036-pin ftsbga devices have been discontinued. 30917 a 30a17 b [0:1] reserved [2] rx_cal_mem_sel 00 enables calendar memory for spi4 rx calendar to be written via mpi. the rx_cal memory encompasses address ranges 0 to 2047. addresses 0 to 1023 are for the main calendar; addresses 1024 to 2047 are for the shadow calendar. spi4 rx calendar memory is write only. [3] rx_pdm_mem_sel enables memory for spi4 rx port descriptors to be read or written via mpi. addresses 0 to 255 valid for this memory. each location contains 3 unused bits, 2 bank_id bits and 3 partition_id bits. [4] tx_cal_mem_sel enables calendar memory for spi4 tx calendar to be written via mpi. the tx_cal memory encompasses address ranges 0 to 2047. addresses 0 to 1023 are for the main calendar; addresses 1024 to 2047 are for the shadow calendar.spi4 tx calendar memory is write only. [5] tx_pdm_mem_sel enables memory for spi4 tx port descriptors to be read or written via mpi. the valid address range is 0 to 1023. the least signi?ant 2 address bits are used as byte enables. 00 accesses the port_id (8 bits) 01 accesses partition_id (3 bits), an unused bit and burst_val (4 bits) 10 accesses 4 unused bits, mb_en (1 bit), m (1 bit), and bank_id (2 bits). the upper 8 bits of address represent the port number being con?ured. [6] tx_cred_mem_se l enables read and write access to tx credits via mpi. the valid memory address range is 0 to 511. the credit for each port is a 10-bit entity. the upper 8 of 9 bits of address select which port to read or write. the lowest bit of address acts as a byte select as follows: 0 accesses the least signi cant 8 bits of the credit eld 1 accesses the most signi cant 2 bits (right-justi ed) of the credit eld [7] tx_stat_mem_sel enables memory for spi4 tx status to be read or written via mpi. this memory used address ranges 0 to 255. each location has six left-most bits unused and two status bits. 30920 a 30a20 b [0:3} tx_dpram_full_t ype_sel 00 full level select for all partitions within bank [0:3]. valid for 32-bit, 64-bit and 128-bit mode. 0 = truly full 1 = 3/4 fifo lines full +1. e.g.: for a fifo size of 32, this value will be (3/4 * 32) + 1 = 25 lines. each line in the fifo is always 128 bits of data irrespec- tive of the aggregation mode [4:7] rx_dpram_empty _type_sel empty level select for all partitions within bank [0:3]. valid for 32-bit, 64-bit and 128-bit mode. 0 = truly empty 1 = 1/4 full - 1. e.g.: for a fifo size of 32, this value will be (1/4 * 32) - 1 = 7 lines. each line in the fifo is always 128 bits of data irrespective of the aggregation mode spi4 core tx control registers (read and write) 30921 a 30a21 b [0:7] tx_cal_m_main 00 number of times the transmit main calendar sequence is repeated between insertions of framing pattern. 30922 a 30a22 b [0:5] reserved [6:7] tx_cal_len_main 00 length of main calendar sequence on the tx status frame. these are the most signi?ant 2 bits of 10 total. 30923 a 30a23 [0:7] tx_cal_len_main length of main calendar sequence on the tx status frame. these are the least signi?ant 8 bits of 10 total. 30924 a 30a24 b [0:7] tx_cal_m_shd 00 number of times the transmit shadow calendar sequence is repeated between insertions of framing pattern. table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 165 1036-pin ftsbga devices have been discontinued. 30925 a 30a25 b [0:5] reserved [6:7] tx_cal_len_shd 00 shadow calendar length for the transmit status frame of spi4. upper 2 bits 30926 30a26 [0:7] tx_cal_len_shd shadow calendar length for the transmit status frame of spi4. lower 8 bits 30927 a 30a27 b [0:1] tx_dpram_0_num fifo 00 number of virtual fifos in tx dpram bank 0 00 = >1 fifo 01 = >2 fifos 10 = >4 fifos 11 = >8 fifos [2:3] tx_dpram_1_num fifo number of virtual fifos in tx dpram bank 1 [4:5] tx_dpram_2_num fifo number of virtual fifos in tx dpram bank 2 [6:7] tx_dpram_3_num fifo number of virtual fifos in tx dpram bank 3 30930 a 30a30 b [0:1] tx_dpram_0_agg r_mode 00 tx bank 0 aggregation mode 00 = 32 bit data 01 = 64-bit data 10 = 128-bit data 11 = not valid [2:3] tx_dpram_1_agg r_mode tx bank 1 aggregation mode [4:5] tx_dpram_2_agg r_mode tx bank 2 aggregation mode [6:7] tx_dpram_3_agg r_mode tx bank 3 aggregation mode 30931 a 30a31 b [0:5] reserved [6:7] tx_max_burst1 00 maximum number of 16-byte bursts expected for any port when its status is starving. these are the 2 most signi?ant bits of a 10-bit number 30932 a 30a32 [0:7] tx_max_burst1 00 maximum number of 16-byte bursts expected for any port when its status is starving. these are the 8 least signi?ant bits of a 10-bit number 30933 a 30a33 b [0:5] reserved [6:7] tx_max_burst2 maximum number of 16-byte bursts expected for any port when its status is hungry. these are the 2 most signi?ant bits of a 10-bit number 30934 a 30a34 b [0:7] tx_max_burst2 00 maximum number of 16-byte bursts expected for any port when its status is hungry. these are the 8 least signi?ant bits of a 10-bit number 30935 a 30a35 b [0:7] tx_data_max_t (byte a) 00 maximum interval between training sequences on the transmit data inter- face. a 32-bit number is formed from 4 bytes organized as {a, b, c, d} and read left to right. when this number is ?? training sequences are disabled. 30936 a 30a36 b [0:7] tx_data_max_t (byte b) 00 maximum interval between training sequences on the transmit data inter- face. a 32-bit number is formed from 4 bytes organized as {a, b, c, d} and read left to right. when this number is ?? training sequences are disabled. 30937 a 30a37 b [0:7] tx_data_max_t (byte c) 00 maximum interval between training sequences on the transmit data inter- face. a 32-bit number is formed from 4 bytes organized as {a, b, c, d} and read left to right. when this number is ?? training sequences are disabled. 30940 a 30a40 b [0:7] tx_data_max_t (byte d) 00 maximum interval between training sequences on the transmit data inter- face. a 32-bit number is formed from 4 bytes organized as {a, b, c, d} and read left to right. when this number is "0", training sequences are disabled. table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 166 1036-pin ftsbga devices have been discontinued. 30941 a 30a41 b [0:7] tx_alpha (byte a) 00 number of times training sequence needs to be repeated every tx_data_max_t cycles. the number is formed from 2 tx_alpha bytes, in the order {a,b}. 30942 a 30a42 b [0:7] tx_alpha (byte b) 00 number of times training sequence needs to be repeated every tx_data_max_t cycles. the number is formed from 2 tx_alpha bytes, in the order {a,b}. 30943 a 30a43 b [0:3] tx_dpram_fifo_o verrun_int_en 00 these bits act as enables for the status ?gs and the interrupts regarding an overrun of the 4 tx dpram fifo banks. [4:7] tx_dpram_fifo_u rrun_int_en 00 these bits act as enables for the status ?gs and the interrupts regarding an underrun of the 4 tx dpram fifo banks. 30944 a 30a44 b [0:4] reserved [5:7] tx_dip2_err_th 00 number of consecutive bad/good dip-2 code words for spi4 tx to lose/gain alignment. loss of alignment is indicated by tx_status_lof_sts 30945 a 30a45 b [0:2] tx_fifo_thresho ld_l 00 low watermark threshold for sync input fifo within tdp. this is used only if min_burst_mode is set. depending on the number of lines in a burst, this threshold should be set to integer[(burst_val/4) + 1] [3:7] tx_fifo_thresho ld_h high watermark threshold for async fifo within tdp to declare a full condi- tion. this causes writes to the tdp to be held off; meaning that an overrun condition can not occur here. spi4 core rx/tx spare controls (read and write) 30946 a 30a46 b [0:7] reserved 00 30908 a 30a08 b [0:7] reserved 00 spi4 core status registers (read only) 30909 a 30a09 b [0:7] reserved 3090a a 30a0a b [0:7] rx_dip4_err_cnt 00 count of dip4 errors. count will reset to ? on a read of this register. if count reaches maximum (255) it will hold. 3090b a 30a0b b [0:7] tx_dip2_err_cnt 00 count of status framing errors. see sip2_err_sts. count will reset to ? after a read of this register. if count reaches maximum (255) it will hold. 3090c a 30a0c b [0:7] rx_dpram_0_fifo _overrun_sts 00 overrun status of bank 0 dpram fifos 0 to 7. these are enabled by rx_dpram_fifo_overrun_int_en[0] (register 30912[a], 30a12[b]). these bits clear when read, but will set immediately if the error condition persists. 3090d a 30a0d b [0:7] rx_dpram_1_fifo _overrun_sts 00 overrun status of bank 1 dpram fifos 0 to 7. these are enabled by rx_dpram_fifo_overrun_int_en[1] (register 30912[a], 30a12[b]). these bits clear when read, but will set immediately if the error condition persists. 3090e a 30a0e b [0:7] rx_dpram_2_fifo _overrun_sts 00 overrun status of bank 2 dpram fifos 0 to 7. these are enabled by rx_dpram_fifo_overrun_int_en[2] (register 30912[a], 30a12[b]). these bits clear when read, but will set immediately if the error condition persists. 3090f a 30a0f b [0:7] rx_dpram_3_fifo _overrun_sts 00 overrun status of bank 3 dpram fifos 0 to 7. these are enabled by rx_dpram_fifo_overrun_int_en[3] (register 30912[a], 30a12[b]). these bits clear when read, but will set immediately if the error condition persists. 30918 a 30a18 b [0:7] rx_dpram_0_fifo _urrun_sts 00 underrun status of bank 0 dpram fifos 0 to 7. these are enabled by rx_dpram_fifo_urrun_int_en[0] (register 30912[a], 30a12[b]). these bits clear when read, but will set immediately if the condition persists. table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 167 1036-pin ftsbga devices have been discontinued. 30919a 30a19b [0:7] rx_dpram_1_fifo _urrun_sts 00 underrun status of bank 1 dpram fifos 0 to 7. these are enabled by rx_dpram_fifo_urrun_int_en[1] (register 30912[a], 30a12[b]). these bits clear when read, but will set immediately if the condition persists. 3091a a 30a1a b [0:7] rx_dpram_2_fifo _urrun_sts 00 underrun status of bank 2 dpram fifos 0 to 7. these are enabled by rx_dpram_fifo_urrun_int_en[2] (register 30912[a], 30a12[b]). these bits clear when read, but will set immediately if the condition persists. 3091b a 30a1b b [0:7] rx_dpram_3_fifo _urrun_sts 00 underrun status of bank 3 dpram fifos 0 to 7. these are enabled by rx_dpram_fifo_urrun_int_en[3] (register 30912[a], 30a12[b]). these bits clear when read, but will set immediately if the condition persists. 3091c a 30a1c b [0] rx_pll_lol_sts 00 status ?g for loss of lock in pll within the spi4 receive core. this ?g is enabled by rx_pll_lol_int_en (register 30913[a], 30a13[b]). [1] rx_bas_done_st s status ?g for spi4 receive core completing the baselining process. base- lining is the self-alignment power-up process that the macro does after it detects lock of the pll. this ?g is enabled by rx_bas_done_int_en. (register 30913[a], 30a13[b]) [2] rx_bas_err_sts status ?g for spi4 receive core failing its internal self-alignment process. this ?g is enables by rx_bas_int_en (register 30913[a], 30a13[b]). [3] rx_dskw_done_s ts status ?g for spi4 receive dynamic alignment complete. this ?g is enabled by rx_dskw_done_int_en. [4] rx_dskw_err_st s status ?g for spi4 receive core failing to dynamically align. this ?g is enabled by rx_dskw_err_int_en (register 30913[a], 30a13[b]). [5] rx_trn_det_sts status ?g for spi4 receive core detecting training patterns. this ?g is enabled by rx_trn_det_int_en (register 30913[a], 30a13[b]). [6] rx_algn_off_st s status ?g for loss of data alignment due to excess consecutive dip4 errors. this ?g is enabled by rx_align_off_int_en (register 30913[a], 30a13[b]). [7] tx_status_lof_s ts status ?g for tx status frame having too many consecutive dip2 errors. this ?g is enabled by tx_status_lof_int_en (register 30913[a], 30a13[b]). 3091d a 30a1d b [0:1] reserved [2] rx_illegal_ctl_ sts 0 status ?g indicating that an illegal control work was received [3:4] reserved [5] rx_dip4_err_sts 00 status ?g for dip4 error [6] tx_dip2_err_sts flag for error in framing tstat[0:1] inputs. this can be an unexpected 11 pattern or a dip2 error. [7] rx_async_fifo_o verrun_sts status ?g for rx fifo overrun inside s4rdp block. spi4 core tx status registers (read and write) 30928 a 30a28 b [0:7] tx_dpram_0_fifo _overrun_sts 00 overrun status of bank 0 tx dpram fifos 0 to 7. these are enabled by tx_dpram_fifo_overrun_int_en[0]. these bits clear when read, but will set immediately if the condition persists. this will happen when writing to the dpram fifos while spi[a,b]_k_fifo_full_j is high. 30929 a 30a29 b [0:7] tx_dpram_1_fifo _overrun_sts 00 overrun status of bank 1 tx dpram fifos 0 to 7. these are enabled by tx_dpram_fifo_overrun_int_en[1]. these bits clear when read, but will set immediately if the condition persists. this will happen when writing to the dpram fifos while spi[a,b]_k_fifo_full_j is high. table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 168 1036-pin ftsbga devices have been discontinued. 3092a a 30a2a b [0:7] tx_dpram_2_fifo _overrun_sts 00 overrun status of bank 2 tx dpram fifos 0 to 7. these are enabled by tx_dpram_fifo_overrun_int_en[2]. these bits clear when read, but will set immediately if the condition persists. this will happen when writing to the dpram fifos while spi[a,b]_k_fifo_full_j is high. 3092b a 30a2b b [0:7] tx_dpram_3_fifo _overrun_sts 00 overrun status of bank 3 tx dpram fifos 0 to 7. these are enabled by tx_dpram_fifo_overrun_int_en[3]. these bits clear when read, but will set immediately if the condition persists. this will happen when writing to the dpram fifos while spi[a,b]_k_fifo_full_j is high. 3092c a 30a2c b [0:7] tx_dpram_0_fifo _urrun_sts 00 underrun status of bank 0 dpram fifos 0 to 7. these are enabled by tx_dpram_fifo_urrun_int_en[0]. these bits clear when read, but will set immediately if the condition persists. 3092d a 30a2d b [0:7] tx_dpram_1_fifo _urrun_sts 00 underrun status of bank 1 dpram fifos 0 to 7. these are enabled by tx_dpram_fifo_urrun_int_en[1]. these bits clear when read, but will set immediately if the condition persists. 3092e a 30a2e b [0:7] tx_dpram_2_fifo _urrun_sts 00 underrun status of bank 2 dpram fifos 0 to 7. these are enabled by tx_dpram_fifo_urrun_int_en[2]. these bits clear when read, but will set immediately if the condition persists. 3092f a 30a2f b [0:7] tx_dpram_3_fifo _urrun_sts 00 underrun status of bank 3 dpram fifos 0 to 7. these are enabled by tx_dpram_fifo_urrun_int_en[3]. these bits clear when read, but will set immediately if the condition persists. memory controller control registers (read and write) 30b00 [0:3] mc_full_thresh old 00 this 4-bit number sets the threshold for the mc_wfifo_full ?g for the write data fifo. example: if the ?ld is 0100, then the mc_wfifo_full ?g will be raised when there are 4 (or fewer) ?led slots remaining in the fifo. [4:7] mc_empty_thres hold this 4-bit number sets the threshold for the mc_rfifo_empty ?g for the read data fifo. example: if the ?ld is 1010, then the mc_rfifo_empty ?g will be raised when there are 10 (or fewer) ?led slots remaining in the fifo. 30b01 [0] mc_rd_dfifo_ur run_int_en 00 enable for memory controller read data fifo underrun status ?g mc_rd_dfifo_urrun_sts, and associated interrupt mem_ctrl1_int. [1] mc_rd_ififo_urr un_int_en enable for memory controller read instruction fifo underrun status ?g mc_rd_ififo_urrun_sts, and associated interrupt mem_ctrl1_int. [2] mc_wr_dfifo_ur run_int_en enable for memory controller write data fifo underrun status ?g mc_wr_dfifo_urrun_sts, and associated interrupt mem_ctrl1_int. [3] mc_wr_ififo_urr un_int_en enable for memory controller write instruction fifo underrun status ?g mc_wr_ififo_urrun_sts, and associated interrupt mem_ctrl1_int. [4] mc_rd_dfifo_ov errun_int_en enable for memory controller read data fifo overrun status ?g mc_rd_dfifo_overrun_sts, and associated interrupt mem_ctrl1_int. hw_issue 23 indicates this should never happen. [5] mc_rd_ififo_ove rrun_int_en enable for memory controller read instruction fifo overrun status ?g mc_rd_ififo_overrun_sts, and associated interrupt mem_ctrl1_int. [6] mc_wr_dfifo_ov errun_int_en enable for memory controller write data fifo overrun status ?g mc_wr_dfifo_overrun_sts, and associated interrupt mem_ctrl1_int. [7] mc_wr_ififo_ove rrun_int_en enable for memory controller write instruction fifo overrun status ?g mc_wr_ififo_overrun_sts, and associated interrupt mem_ctrl1_int. table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 169 1036-pin ftsbga devices have been discontinued. 30b02 [0:6] reserved [7] mc_id_err_int_e n enable for incoherent data and instruction words status ?g mc_id_err_sts, and associated interrupt mem_ctrl2_int. 30b03 [0] mc_burst_mode 00 0 = 2-word burst 1 = 4-word burst [1] reserved [2:3] mc_ick_sel input clock selector: 00 = mcrefclk (hstl) 01 = btrefclk (spia reference, lvttl) 10 = atrefclk (spib reference, lvttl) 11 = f_mc_refclk (fpga) [4:6] reserved [7] mc_ock_sel 00 selects between input clock divided by 2, or pll output for source of pmic/pmicn: 0 = input clock 1 = pll 30b04 [0] reserved [1:3] pll_n 00 numerator of multiplier factor for frequency of pll output clock: ck2x = mc_ick * (pll_n / pll_m) [4] reserved [5:7] pll_m 00 denominator of multiplier factor for frequency of pll output clock: ck2x = mc_ick * (pll_n / pll_m) 30b05 [0:7} reserved 30b06 [0:7] reserved memory controller status registers (read only) 30b08 [0] mc_rd_dfifo_ur run_sts 00 status ?g for read data fifo underrun. enabled by mc_rd_dfifo_urrun_int_en [1] mc_rd_ififo_urr un_sts status ?g for read instruction fifo underrun. enabled by mc_rd_ififo_urrun_int_en [2] mc_wr_dfifo_ur run_sts status ?g for write data fifo underrun. enabled by mc_wr_dfifo_urrun_int_en [3] mc_wr_ififo_urr un_sts status ?g for write instruction fifo underrun. enabled by mc_wr_ififo_urrun_int_en [4] mc_rd_dfifo_ov errun_sts status ?g for read data fifo overrun. enabled by mc_rd_dfifo_overrun_int_en [5] mc_rd_ififo_ove rrun_sts status ?g for read instruction fifo overrun. enabled by mc_rd_ififo_overrun_int_en [6] mc_wr_dfifo_ov errun_sts status ?g for write data fifo overrun. enabled by mc_wr_dfifo_overrun_int_en [7] mc_wr_ififo_ove rrun_sts status ?g for write instruction fifo overrun. enabled by mc_wr_ififo_overrun_int_en 30b09 [0:6] reserved [7] mc_id_err_sts 00 status ?g for incoherent data and instruction words. enabled by mc_id_err_int_en. 30b0a [0:7] reserved table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 170 1036-pin ftsbga devices have been discontinued. common control registers (read and write) 30b20 [0:3] reserved [4] hard_reset_fc 00 hard reset for serdes block. when set to 1, disabled serdes logic by resetting it. same functionality as interface signal fpga_reset_fc [5] soft_reset_mc software reset for memory controller block [6] soft_reset_s4a software reset for spia block [7] soft_reset_s4b software reset for spib block 30b21 [0:6] com_spare_c 00 spare common control bits [7] force_int force all the enabled status and interrupt bits common status registers (read and write) 30b28 [0:7] reserved reserved 30b29 [0] serdes_int 00 signals that an enabled interrupt has come from the serdes. this is cleared when read and will only reassert when the underlying event goes away and comes back. [1] mem_ctrl2_int signals that an enabled interrupt has come from the memory controller other than the fifos. this is cleared when read and will only reassert when the underlying event goes away and comes back. [2] mem_ctrl1_int signals that an enabled interrupt has come from the memory controller fifos. this is cleared when read and will only reassert when the underlying event goes away and comes back. [3] dpram_int signals that an enabled interrupt has come from one of the dpram fifo banks. this is cleared when read and will only reassert when the underlying event goes away and comes back. [4] spi_b_cor2_int signals that an enabled interrupt has come from the register 30a1d. this is cleared when read and will only reassert when the underlying event goes away and comes back. [5] spi_b_cor1_int signals that an enabled interrupt has come from register 30a1c. this is cleared when read and will only reassert when the underlying event goes away and comes back. [6] spi_a_cor2_int signals that an enabled interrupt has come from register 3091d. this is cleared when read and will only reassert when the underlying event goes away and comes back. [7] spi_a_cor1_int signals that an enabled interrupt has come from register 3091c. this is cleared when read and will only reassert when the underlying event goes away and comes back. table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 171 1036-pin ftsbga devices have been discontinued. 30b2a [0] tx_int_b 00 signals that an enabled interrupt has come from tx dpram fifos for spi4 core b. this is cleared when read and will only reassert when the underlying event goes away and comes back. [1] rx_int_b signals that an enabled interrupt has come from rx dpram fifos for spi4 core b. this is cleared when read and will only reassert when the underlying event goes away and comes back. [2] tx_int_a signals that an enabled interrupt has come from tx dpram fifos for spi4 core a. this is cleared when read and will only reassert when the underlying event goes away and comes back. [3] rx_int_a signals that an enabled interrupt has come from rx dpram fifos for spi4 core b. this is cleared when read and will only reassert when the underlying event goes away and comes back. [4] bank_3_int signals that an enabled interrupt has come from dpram bank 3 fifos (or both spi4 blocks, both tx and rx ?gs). this is cleared when read and will only reassert when the underlying event goes away and comes back. [5] bank_2_int signals that an enabled interrupt has come from dpram bank 2 fifos (or both spi4 blocks, both tx and rx ?gs). this is cleared when read and will only reassert when the underlying event goes away and comes back. [6] bank_1_int signals that an enabled interrupt has come from dpram bank 1 fifos (or both spi4 blocks, both tx and rx ?gs). this is cleared when read and will only reassert when the underlying event goes away and comes back. [7] bank_0_int signals that an enabled interrupt has come from dpram bank 0 fifos (or both spi4 blocks, both tx and rx ?gs). this is cleared when read and will only reassert when the underlying event goes away and comes back. 30b2b [0:7] com_spare_s 00 spare common status bits embedded control memory access (31000-31fff) 31000 [0:7] data[7:0] 00 embedded control memories are accessed when register addresses 3100- 31fff are written or read. the address passed to the embedded memories is the lower 12 bits of the register address. writing to a register address in this range causes data to be transferred to the selected embedded memo- ries. more than one memory can be written with a single operation by having multiple select bits active. the select bits are 30917 and 30a17 registers. reading from a register address in this range causes the data in the mem- ory selected to appear. the following priority rules apply to the selection of which memory is read from. (1) 30917 bits take precedence over bits in the 30a17 register. (2) lower bit numbers take precedence over higher bit numbers within a reg- ister. table 47. memory map (continued) (0x) abso- lute address bit name reset value (0x) description lattice semiconductor orca orspi4 data sheet 172 1036-pin ftsbga devices have been discontinued. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. the orca series 4 fpscs include circuitry designed to protect the chips from damaging substrate injection cur- rents and to prevent accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress table 48. absolute maximum ratings. parameter symbol min. max. unit storage temperature t stg -65 150 ? power supply voltage with respect to ground v dd33 - 0.3 4.2 v v dd33_fpgapll -0.3 4.2 v v dd15 -0.3 2.0 v v ddio - 0.3 4.2 v spi4 voltages with respect to ground v dda_spia -0.3 2.0 v v dda_spib -0.3 2.0 v v dda_spic -0.3 2.0 v v dda_spid -0.3 2.0 v memory controller voltages with respect to ground v ddh -0.3 2.0 v v dd_pll -0.3 4.2 v serdes supply voltages v dd_ana -0.3 2.0 v v ddgb -0.3 2.0 v fpga input signal with respect to ground v in v ss ?0.3 v dd io + 0.3 v fpga signal applied to high-impedance output v ss ?0.3 v dd io + 0.3 v maximum package body (soldering) temperature 220 ? lattice semiconductor orca orspi4 data sheet 173 1036-pin ftsbga devices have been discontinued. recommended operating conditions table 49. recommended operating conditions parameter symbol min. max. unit power supply voltage with respect to ground 1 v dd33 3.0 3.6 v v dd33_fpgapll 3.0 3.6 v v dd15 1.425 1.575 v spi4 voltages with respect to ground v dda_spia 1.425 1.575 v v dda_spib 1.425 1.575 v v dda_spic 1.425 1.575 v v dda_spid 1.425 1.575 v memory controller voltages with respect to ground v ddh 2 1.425 1.575 v ref_1 0.64 0.87 v ref_2 0.64 0.87 v ref_3 0.64 0.87 v ref_4 0.64 0.87 v v dda_pll 3.0 3.6 v serdes supply voltage v dd_ana 1.425 1.575 v v ddgb 1.425 1.575 v serdes cml i/o supply voltages v ddib 1.425 1.89 v v ddob 1.425 1.89 v fpga input voltage v_ in v ss -0.3 v ddio to +0.3 v memory controller input voltage 2 v_ iwmctrl v ss -0.3 1.89 v junction temperature t j ?40 125 ? 1. for fpga recommended operating conditions and electrical characteristics, see the recommended operating conditions and electr i- cal characteristics tables in the orca series 4 fpga data sheet (or4e06) and the orca series 4 i/o buffer technical note. 2 memory controller 1.8v tolerant with vddh = 1.5v ?5% lattice semiconductor orca orspi4 data sheet 174 1036-pin ftsbga devices have been discontinued. orspi4 power tables table 50. orspi4 post-con?uration standby current * conditions: t a = 85 c, vdd15 = 1.575v, vdd33 = 3.6v, vddio = 3.6v, internal oscillator running, no output loads, inputs vddio or vss. standby current is tested with the embedded core in a powered down state. table 51. orspi4 combined spia and spib worst case power table * power measured with both spia and spib operating simultaneously. ac power only. power numbers do not include post-con?uratio n standby current (see table 50). fpga power not included. fpga power is application dependent ?see the orca series 4 data sheet to calculate fpga power. conditions: t a = 85 c, vdd15 = 1.575v, vdd33 = 3.6v, vddio = 3.6v. table 52. orspi4 qdr memory controller worst case power table note: in many applications the pll can be disabled to reduce power. temperature: -40 c to 125 c, power supplies: vdd15, vddh = 1.575v, vdd33 = 3.6v, data pattern: prbs 2^31-1 parameter clock frequency unit vdd15* vdd33* vddh post-con?uration standby current 500 300 200 ma parameter reference clock frequency vdd15 vdda_spi[a:d] power* vdd33 power* power per spi interface* unit 450 mhz (900 mbps) with dynamic alignment frequency 112.5 mhz total 0.887 0.518 1.405 w 325 mhz (650 mbps) with static alignment frequency 81.25 mhz total 0.570 0.486 1.056 w 311 mhz (622 mbps) with static alignment frequency 77.75 mhz total 0.513 0.493 1.006 w 100 mhz (200 mbps) quarter rate frequency 200 mhz total 0.082 0.436 0.518 w 78 mhz (156 mbps) quarter rate frequency 156 mhz total 0.017 0.407 0.424 w parameter value unit clock frequency 160 mhz vdd15, vddh power 226.8 mw vdd33 power 46.8 mw total power 273.6 mw lattice semiconductor orca orspi4 data sheet 175 1036-pin ftsbga devices have been discontinued. table 53. orspi4 serdes worst case power table 1. with all channels operating, temperature: -40 c to 125 c, power supplies: v dd_ana , v ddib , v ddob = 1.575v, data pattern: prbs 2^31-1 2. with orspi4 cml output buffers connected to orspi4 cml input buffers. actual power dissipation can vary depending on the ter mination used. parameter operating frequency vdd15 1, 2 units serdes, mux/demux, align fifo and i/o (per channel) 1.25 ghz 195 mw serdes, mux/demux, align fifo and i/o (per channel) 2.5 ghz 210 mw serdes, mux/demux, align fifo and i/o (per channel) 3.125 ghz 225 mw 8b/10b encoder/decoder (per channel) 3.125 ghz 50 mw lattice semiconductor orca orspi4 data sheet 176 1036-pin ftsbga devices have been discontinued. spi4 electrical and timing characteristics spi4 lvds i/o table 54. driver dc data* table 55. receiver dc data 1 table 56. spi4 lvds operating parameters parameter symbol test conditions min. typ. max. units output voltage high, v oa or v ob v oh r load = 100 ?1% 1.475 ? v output voltage low, v oa or v ob v ol r load = 100 ?1% 0.925 ? v output differential voltage ? v od ? r load = 100 ?1% 0.25 0.45 ? v output offset voltage v os r load = 100 ?1% 1.125* 1.275 ? v output impedance, differential r o v cm = 1.0 v and 1.4 v 80 100 120 w r o mismatch between a and b r o v cm = 1.0 v and 1.4 v 10 % change in differential voltage between complementary states ? v od ? r load = 100 ?1% 25 mv change in output offset voltage between complementary states v os r load = 100 ?1% 25 mv output current i sa, i sb driver shorted to gnd 24 ma output current i sab drivers shorted together 12 ma power-off output leakage |ixa|, |ixb| v dd = 0 v v pa d , v padn = 0 v?.5 v 10 ma 1. v dd 33 = 3.1 v?.5 v, v dd 15 = 1.4 v?.6 v, ?0 ?c. 2. external reference, ref10 = 1.0 v ?3%, ref14 = 1.4 v ?3%. parameter symbol test conditions min. typ. max. units input voltage range, via or vib v i ? v gpd ? < 925 mv dc ?1 mhz 0.0 1.2 2.4 v input differential threshold v idth ? v gpd ? < 925 mv 450 mhz ?00 100 mv input differential hysteresis v hyst (+v idthh ) ?(? idthl )25 mv receiver differential input impedance r in with build-in termination, center-tapped 80 100 120 1. v dd = 3.1v - 3.5v, 0 ? - 125 ? . parameter test conditions min. normal max. units transmit termination resistor 80 100 120 . receiver termination resistor 80 100 120 . note: under worst-case operating conditions, the lvds driver will withstand a disabled or unpowered receiver for an unlimited p eriod of time without being damaged. similarly, when outputs are short-circuited to each other or to ground, the lvds will not suffer permane nt damage. the lvds driver supports hot insertion. under a well-controlled environment, the lvds i/o can drive backplane as well as cable. lattice semiconductor orca orspi4 data sheet 177 1036-pin ftsbga devices have been discontinued. figure 88. output buffer delays table 57. lvds driver ac data 1 termination resistor the lvds drivers and receivers operate at 100 differential impedance, as shown below. external resistors are not required. the differential driver and receiver buffers include termination resistors inside the device package, as shown in fig ure 89 below. the center tap inputs should be connected to ground via a .01 pf capacitor. figure 89. spi4 lvds driver and receiver and associated internal components parameter symbol test conditions min. typ. max. units v od fall time, 80% to 20% t f z l = 100 ?1% c pa d = 3.0 pf, c pad = 3.0 pf 100 210 ps v od rise time, 20% to 80% t r z l = 100 ?1% c pad = 3.0 pf, c pad = 3.0 pf 100 210 ps differential skew |t phla ?t plhb | or |t phlb ?t plha |t skew1 any differential pair on pack- age at 50% point of the tran- sition 50 ps 1. v dd 33 = 3.1v - 3.5 v, v dd 15 = 1.4v - 1.6 v, -40?c. pa d out pa d out 3pf 3pf ts[i] out[i] lvds receiver 50 lvds driver 100 50 center tap external device pins lattice semiconductor orca orspi4 data sheet 178 1036-pin ftsbga devices have been discontinued. spi4 ac timing supported data rates the spi4 interfaces (spia and spib) on the orspi4 device support the following data rates table 58. supported data rates 1 spi[a,b]_trefclk_x8 internal signal is used in quarter-rate mode spi4.2 data interface system timing reference points figure 90 shows the system timing reference points a and b for the data path timing parameters for both the trans- mit interface and the receive interface. figure 90. system timing reference points. figure 91 de?es the timing parameters t dia and t dib which show the relationship of tdclk to tdat generated by the orspi4 transmit interface. values of t dia and t dib are given in table 59. figure 91. spi4.2 transmit timing points with respect to clock edge data rate clock frequency (ddr) transmit refclk frequency recommended operating mode 500 -900 mbps 250 - 450 mhz 62.5 - 112.5 mhz dynamic 500 -650 mbps 250 - 325 mhz 62.5 - 81.25 mhz static 100 - 200 mbps 50 - 100 mhz 100 - 200 mhz 1 quarter-rate static mode source sink tdat[15:0] / rdat[15:0} tctl/rctl tdclk/rdclk ab tdclk tdat (a) launch edge t dia t dib d tdclk lattice semiconductor orca orspi4 data sheet 179 1036-pin ftsbga devices have been discontinued. table 59. spi4.2 transmit data interface timing figure 92 de?es the timing parameters t s and t h which show the setup and hold requirements at the orspi4 receive interface when in static mode, which are dependent on the spi_dlytap register settings chosen. values of t s and t h at all values of spi_dlytap are given in table 60. figure 92. spi4.2 receive timing points with respect to clock edge symbol description min max units t dia orspi4 transmit data (tdat[15:0], tctl) invalid window before clock edge (source a) ?ps t dib orspi4 transmit data (tdat[15:0], tctl) invalid window after clock edge (source a) 400 ps d tdclk tdclk duty cycle 45% 55% tdclk period rdclk rdat (b) capture edge t s t h spi_dlytap_a,b[2:0]=0 spi_dlytap_a,b[2:0]=4 spi_dlytap_a,b[2:0]=7 t s t s t h t h lattice semiconductor orca orspi4 data sheet 180 1036-pin ftsbga devices have been discontinued. table 60. spi4.2 receive data interface timing note: receive data = rdat[15:0], rctl. symbol description min max units t s orspi4 receive data setup time with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=0 60 ps orspi4 receive data setup time with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=1 -20 ps orspi4 receive data setup time with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=2 -80 ps orspi4 receive data setup time with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=3 -150 ps orspi4 receive data setup time with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=4 -220 ps orspi4 receive data setup time with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=5 -280 ps orspi4 receive data setup time with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=6 -360 ps orspi4 receive data setup time with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=7 -430 ps t h orspi4 receive data hold with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=0 790 ps orspi4 receive data hold with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=1 870 ps orspi4 receive data hold with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=2 970 ps orspi4 receive data hold with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=3 1050 ps orspi4 receive data hold with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=4 1120 ps orspi4 receive data hold with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=5 1210 ps orspi4 receive data hold with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=6 1290 ps orspi4 receive data hold with respect to clock capture edge (sink b) spi_dlytap_a,b[2:0]=7 1370 ps lattice semiconductor orca orspi4 data sheet 181 1036-pin ftsbga devices have been discontinued. the static timing budget for a data transfer between two orspi4 devices at a data rate of 650 mbps in shown in table 61. table 61. data path interface timing example for static alignment (orspi4 to orspi4) note 1: orspi4 transmit speci?ation note 2: orspi4 receive speci?ation description value unit tdclk/rdclk frequency 325 mhz before reference point a 1 clock to data skew, clock duty cycle distortion, data duty cycle distortion, data jittert dia + t dib 400 ps between reference points a and b data to data skew, relative jitter 100 ps subtotal g max 500 ps after reference point b device setup and hold 2 940 ps sampling error 50 ps total 1490 ps total 650 mbps bit period 1540 ps available margin 50 ps lattice semiconductor orca orspi4 data sheet 182 1036-pin ftsbga devices have been discontinued. the dynamic alignment timing budget for a data transfer between two orspi4 devices is shown in table 62. table 62. data path parameters for dynamic alignment. with prbs 2^7-1 data pattern, all channels operating, fpga logic active, 900 mbit/s data rate with 112.5 mhz refclk, refclk jit ter of 30 ps, t j = -40?c to 125?c, 1.425 v to 1.575 v supply. jitter measured with a wavecrest sia-3000. spi4.2 status interface system timing reference points figure 93 shows the system timing reference points a and b for status channel timing parameters listed in table 63. figure 93. status channel reference points figure 94. status channel reference points with respect to clock edge (lvds and lvttl i/os) description value (ui peak-to-peak) transmit clock jitter 0.11 transmit data jitter with respect to clock edge 0.09 receive clock jitter tolerance 0.60 source sink tstat[1:0] / rstat[1:0] tsclk/rsclk dc note: only status signals are shown rsclk rstat (c) launch edge t dia t dib (d) capture edge t s t h tsclk tstat lattice semiconductor orca orspi4 data sheet 183 1036-pin ftsbga devices have been discontinued. table 63. status path interface orspi4 timing in centered (oif) mode note: this table compares the oif speci?ation requirements vs. the orspi4 speci?ation. there is no oif speci?ation for lvds buffers. figure 95. orspi4 static mode status signals data capture (reference point d) oif-spi4-02.0 speci?ation requirements orspi4 timing in centered (oif) mode symbol description min max min max units f d tdclk/rdclk frequency 450 450 mhz f s tsclk/rsclk frequency 112.5 112.5 mhz tsclk/rsclk duty cycle 40 60 40 60 % t dia rstat invalid with respect to clock edge (reference point c) 2.5 0.30 ns t dib rstat invalid with respect to clock edge (reference point c) 1.0 0.45 ns t s setup time for tstat with respect to tsclk - lvttl buffers (reference point d) 2.0 1.0 ns setup time for tstat with respect to tsclk - lvds buffers (reference point d) 1.0 ns t h hold time for tstat with respect to tsclk - lvttl buffers (reference point d) 0.5 0.5 ns hold time for tstat with respect to tsclk - lvds buffers (reference point d) 0.7 ns reference point d tstat/ r s tat lvttl 0 1 d lvds status_io_sel tsclk/ rsclk lvttl 0 1 0 1 lvds spi_stam lattice semiconductor orca orspi4 data sheet 184 1036-pin ftsbga devices have been discontinued. figure 96. status channel reference points with respect to clock edge (edge aligned legacy mode) table 64. status path interface orspi4 timing in legacy mode note: this table compares the oif speci?ation requirements vs. the orspi4 speci?ation. there is no oif speci?ation for lvds buffers. orspi4 timing in legacy mode symbol description min max units f d tdclk/rdclk frequency 450 mhz f s tsclk/rsclk frequency 112.5 mhz tsclk/rsclk duty cycle 40 60 % t dia data invalid window with respect to clock edge (reference point c) 0.3 ns t dib data invalid window with respect to clock edge (reference point c) 0.45 ns t s * setup time for tstat with respect to tsclk - lvttl buffers (reference point d) 0.5 ns setup time for tstat with respect to tsclk - lvds buffers (reference point d) 0.7 ns t h * hold time for tstat with respect to tsclk - lvttl buffers (reference point d) 1.2 ns hold time for tstat with respect to tsclk - lvds buffers (reference point d) 1.0 ns rsclk rstat (c) launch edge t dia t dib (d) capture edge t s t h tsclk tstat lattice semiconductor orca orspi4 data sheet 185 1036-pin ftsbga devices have been discontinued. serdes electrical and timing characteristics serdes high speed data transmitter table 65 speci?s serial data output buffer parameters measured on devices with typical and worst case process parameters and over the full range of operation conditions. table 65. serial output timing and levels (cml i/o) transmitter output jitter is a critical parameter to systems with high-speed data links. table 66 and table 67 specify the transmitter output jitter for typical and worst case devices over the full range of operating conditions. table 66. channel output jitter (3.125 gbits/s) table 67. channel output jitter (2.5 gbits/s) parameter min. typ. max. units rise time (20%?0%) 50 80 110 ps fall time (80%?0%) 50 80 110 ps common mode v dd ob ?0.30 v dd ob ?0.25 v dd ob ?0.15 v differential swing (full amplitude) 1 600 700 1000 mv p-p differential swing (half amplitude) 1 300 350 500 mv p-p output load (external) 86 . 1. differential swings are measured at the end of 3 inches of fr-4 and 12 inches of coax cable. parameter min. typ. 1 max. 1 units deterministic 0.13 0.24 ui p-p random 0.06 0.12 ui p-p total 2, 3 0.19 0.36 ui p-p 1. with prbs 2^7-1 data pattern, all channels operating, fpga logic active, refclk jitter of 30 ps., 0 o c to 85 o c, 1.425 v to 1.575 v supply. 2. wavecrest sia-3000 instrument used to measure one-sigma (rms) random jitter component value. this value is multiplied by 14 t o provide the peak-to-peak value that corresponds to a ber of 10 -12 . 3. total jitter measurement performed with wavecrest sia-3000 at a ber of 10 -12 . see instrument documentation and other wavecrest publi- cations for a detailed discussion of jitter types included in this measurement. parameter min. typ. 1 max. 1 units deterministic 0.12 0.15 ui p-p random 0.06 0.16 ui p-p total 2, 3 0.18 0.31 ui p-p 1. with prbs 2^7-1 data pattern, all channels operating, fpga logic active, refclk jitter of 30 ps., 0 o c to 85 o c, 1.425 v to 1.575 v supply. 2. wavecrest sia-3000 instrument used to measure one-sigma (rms) random jitter component value. this value is multiplied by 14 t o provide the peak-to-peak value that corresponds to a ber of 10 -12 . 3. total jitter measurement performed with wavecrest sia-3000 at a ber of 10 -12 . see instrument documentation and other wavecrest publi- cations for a detailed discussion of jitter types included in this measurement. lattice semiconductor orca orspi4 data sheet 186 1036-pin ftsbga devices have been discontinued. serdes high speed data receiver table 68 speci?s receiver parameters measured on devices with worst case process parameters and over the full range of operation conditions. table 68. external data input speci?ations input data jitter tolerance a receiver's ability to tolerate incoming signal jitter is very dependent on jitter type. high speed serial interface stan- dards have recognized the dependency on jitter type and have recently modi?d speci?ations to indicate toler- ance levels for different jitter types as they relate to speci? protocols (e.g xaui, fc, in?iband etc.). sinusoidal jitter is considered to be a worst case jitter type. table 69 shows receiver speci?ations with 10 mhz sinusoidal jit- ter injection. xaui speci? jitter tolerance measurements were measured in a separate experiment detailed in tech- nical note tn1032, serdes test chip jitter, and are not re?cted in these results. table 69. receiver sinusoidal jitter tolerance speci?ations parameter conditions min. typ. max. units input data stream of nontransitions 8b/10b encode/decode off 72 bits sensitivity (differential), worst-case 1 3.125 gbps 80 mvp-p input levels 2 ? ss - 0.3 v dd_ana + 0.3 v internal buffer resistance (each input to vddib) 40 50 60 . pll lock time 3 note 3 1. with prbs 2^7-1 data pattern, all channels operating, fpga logic active, refclk jitter of 30 ps., t a = 0 o c to 85 o c, 1.425 v to 1.575 v sup- ply. 2. input level min + (input peak to peak swing)/2 common mode input voltage input level max - (input peak to peak swing)/2 3. the orspi4 serdes receiver performs four levels of synchronization on the incoming serial data stream, providing ?st bit, th en byte (character), then channel (32-bit word), and ?ally optional multi-channel alignment as described in tn1025. the pll lock time is the time required for the cdr pll to lock to the transitions in the incoming high-speed serial data stream. if the pll is unable to lock to the serial data stream, it instead locks to refclk to stabilize the voltage-controlled oscillator (vco), and periodically switches back to the serial data stream to again attempt synchronization. parameter conditions max. unit input data jitter tolerance @ 3.125 gbps, typical 600 mv diff eye 1 0.75 u ip-p jitter tolerance @ 3.125 gbps, worst case 600 mv diff eye 1 0.65 u ip-p jitter tolerance @ 2.5 gbps, typical 600 mv diff eye 1 0.79 u ip-p jitter tolerance @ 2.5 gbps, worst case 600 mv diff eye 1 0.67 u ip-p 1. with prbs 2^7-1 data pattern, all channels operating, fpga logic active, refclk jitter of 30 ps., t a = 0 o c to 85 o c, 1.425 v to 1.575 v supply. jitter measured with a wavecrest sia-3000. lattice semiconductor orca orspi4 data sheet 187 1036-pin ftsbga devices have been discontinued. input eye-mask characterization figure 97 provides an eye-mask characterization of the serdes receiver input. the eye-mask is speci?d below for two different eye-mask heights. it provides guidance on a number of input parameters, including signal ampli- tude and rise time limits, noise and jitter limits, and p and n input skew tolerance. almost all detrimental character- istics of transmit signal and the interconnection link design result in eye-closure. this, combined with the eye- opening limitations of the line receiver, can provide a good indication of a link s ability to transfer data error-free. the clock and data recovery (cdr) portion of the orspi4 serdes receiver has the ability to ?ter incoming sig- nal jitter that is below the clock recovery pll bandwidth (about 3 mhz). the eye-mask speci?ations of table 70 are for jitter frequencies above the pll bandwidth of the cdr, which is a worst case condition. when jitter occurs at frequencies below the pll bandwidth, the receiver jitter tolerance is signi?antly better. for this case error-free data detection can occur even with a completely closed eye-mask. figure 97. receive data eye-diagram template (differential) table 70. receiver eye-mask speci?ations 1 parameter conditions value unit input data eye opening width (h) @ 3.125 gbps v=175 mv diff 1 0.55 u ip-p eye opening width (t) @ 3.125 gbps v=175 mv diff 1 0.15 u ip-p eye opening width (h) @ 3.125 gbps v=600 mv diff 1 0.35 u ip-p eye opening width (t) @ 3.125 gbps v=600 mv diff 1 0.10 u ip-p eye opening width (h) @ 2.5 gbps v=175 mv diff 1 0.42 u ip-p eye opening width (t) @ 2.5 gbps v=175 mv diff 1 0.15 u ip-p eye opening width (h) @ 2.5 gbps v=600 mv diff 1 0.33 u ip-p eye opening width (t) @ 2.5 gbps v=600 mv diff 1 0.10 u ip-p 1. with prbs 2^7-1 data pattern, 10 mhz sinusoidal jitter, all channels operating, fpga logic active, refclk jitter of 30 ps., t a = 0 o c to 85 o c, 1.425 v to 1.575 v supply. h v 1.2 v ui t lattice semiconductor orca orspi4 data sheet 188 1036-pin ftsbga devices have been discontinued. serdes external reference clock the external reference clock selection and its interface are a critical part of system applications for this product. table 71 speci?s reference clock requirements, over the full range of operating conditions. the designer is encourage to read tn1040, serdes reference clock, which discusses various aspects of this system element and its interconnection. table 71. reference clock speci?ations (refclkp and refclkn) serdes core timing characteristics table 72 summarizes the end-to-end latencies through the embedded core for the various modes. all latencies are given in clock cycles for system clocks at half the refclk_[a:b] frequency. for a refclk_[a:b] of 156.25 mhz, a system clock cycle is 6.4 ns. table 72. signal latencies, embedded core parameter min. typ. max. units frequency range 60 185 mhz frequency tolerance 1 -350 350 ppm duty cycle (measured at 50% amplitude point) 40 50 60 % rise time 500 1000 ps fall time 500 1000 ps p? input skew 75 ps differential amplitude 500 800 2 x v ddib mv p-p common mode level v single-ended/2 0.75 v dd 15 ?(v single-ended/2 )v single-ended amplitude 250 400 v ddib mv p-p input capacitance (at refclkp) 5 pf input capacitance (at reclkn) 5 pf 1. this speci?ation indicates the capability of the high-speed receiver cdr pll to acquire lock when the reference clock frequ ency and incoming data rate are not synchronized. operating mode signal latency (max.) transmit path 5 clock cycles receive path multi-channel alignment bypassed 1 4.5 clock cycles with multi-channel alignment 1 13.5-22.5 clock cycles 1. with multi-channel alignment, the latency is largest when the skew between channels is at the maximum that can be correctly compensated for (18 clock cycles). the latency speci?d in the table is for data from the channel received ?st. lattice semiconductor orca orspi4 data sheet 189 1036-pin ftsbga devices have been discontinued. memory controller electrical and timing characteristics hstl class i and class ii hstl (high-speed transceiver logic) - jedec standard jes 8-6 (august 1995), is a technology independent interface standard for digital integrated circuits. it is a voltage scalable and technology independent i/o structure. the i/o structures required by this standard contain a reference receiver (typically 50% of the vddh), described as a refi for single-ended inputs and outputs using power supply inputs (vddh) that may differ from those operating the device itself. this buffer is designed to receive hstl signal levels from devices wtih1.5v hstl i/os. hstl also allows chips with different power supplies to easily communicate with each other. table 73. hstl class ii dc operating speci?ations 1. 50% vddh 2. vddh - 400 mv. class parameter condition min typical max unit vddh -- 1.425 1.5 1.575 v refi 1 -- 0.64 0.75 0.87 v vterm 1 -- -- 0.75 - v vih -- refi + 100mv 0.85 vddh + 0.3 v vil -- -0.3 0.65 refi -100 mv v class 1 voh 2 ioh > 8 ma vddh - 0.4 1.1 -- v vol iol > -8 ma -- -- 0.4 v class 2 voh 2 ioh > 16 ma vddh - 0.4 1.1 -- v vol iol > -16 ma -- -- 0.4 v lattice semiconductor orca orspi4 data sheet 190 1036-pin ftsbga devices have been discontinued. figure 98. hstl termination scheme note: refer to technical note tn1046 for more detailed board design guidelines for the orspi4 qdr memory controller. orspi4 qdr memory device * ext_1k vddh (1.5v) vddmem_io (1.5v) vterm = z = 50 ohm z = 50 ohm 50 ohm 50 ohm 1.5 kohm * refer to memory specification for specific terminations vddh (1.5v) vddmem_io (1.5v) vterm = z = 50 ohm z = 50 ohm 75 ohm 75 ohm pmik(n) & pmic(n) signals pmid, pmia, pmiwn, pmirn & pmiq signals vddh 2 refi = vddh 2 refi = 25 ohm vddh 2 vddh 2 vddmem_io 2 vddmem_io 2 vddmem_io 2 vddmem_io 2 hstl-ii output buffer hstl-ii output buffer lattice semiconductor orca orspi4 data sheet 191 1036-pin ftsbga devices have been discontinued. supported data rates the memory controller on the orspi4 device can support the following data rates. table 74. supported data rates (36-bit qdr-ii, 32 bit considered data) 1. data rate = (max. write data rate + max. read data rate) for 32 bits of data. 2. characterized with 200 mhz rated qdr-ii sram devices with their dll enabled. duty cycle of pmic and pmicn signals was close to 50%. 3. assumes board trace lengths of 3 inches or less. memory controller input/output timing speci?ation figure 99. memory controller output timing speci?ations table 75. memory controller output timing speci?ations data rate -1 -2 -3 clock frequency (ddr) data rate 1, 2 clock frequency (ddr) data rate 1, 2 clock frequency (ddr) data rate 1, 2 156 mhz 19.97 gbps 3 165 mhz 21.12 gbps 3 175 mhz 22.40 gbps 3 symbol description min value max value units t ai pmik to previous address invalid 1.2 ns t av pmik to address valid 2.0 ns t di pmik to previous data invalid 1.0 ns t dv pmik to data valid 2.65 ns d pmik(n) pmik/pminkn duty cycle 40% 60% pmik/pmikn clock cycle pmikn pmia t ai pmid t av t di t dv pmik d pmik(n) lattice semiconductor orca orspi4 data sheet 192 1036-pin ftsbga devices have been discontinued. figure 100. memory controller input timing speci?ations table 76. memory controller input timing speci?ations symbol description min value units t rs pmiq data in setup with respect to pmic clock rising edge -0.5 ns t rh pmiq data in hold with respect to pmic clock rising edge 2.0 ns t fs pmiq data in setup with respect to pmicn clock rising edge -0.5 ns t fh pmiq data in hold with respect to pmicn clock rising edge 2.0 ns pmicn pmiq t rs t rh t fs t rs pmic lattice semiconductor orca orspi4 data sheet 193 1036-pin ftsbga devices have been discontinued. power supplies for orspi4 power supply descriptions table 77 shows the orspi4 fpga and embedded core power supply groupings. vdd33 is a 3.3v positive power supply used for 3.3 v con?uration rams. vdd33_fpgapll is a 3.3v positive power supply for internal plls. when using plls, this power supply should be well isolated from all other power supplies on the board for proper operation. the ?e vddio supplies are positive power supply used by the fpga i/o banks. the 1.5 volt digital power supplies are used for the fpga and the embedded core transmit and receive digital logic including the microprocessor logic. the 1.5 volt analog power supply is used for serdes high-speed analog circuitry in the embedded core between the i/o buffers and the digital logic. the serdes vddib and vddob power supplies can be independently set to 1.5 v or 1.8 v, depending on the end application. the serdes guard band supplies are independent connection brought out to pins. table 77. power supplies the orspi4 spi4 embedded core requires an isolated 1.5v supply connected to four dedicated vdda_spi[a:d] pins. this supply is used to power the analog circuitry of the core between the lvds i/o and the digital logic. the lvds bus also requires connections to pins used for ac center-tap termination. the dedicated lvctap pins should be connected to gnd through a 0.01 ufd capacitor. the qdr memory controller portion of the embedded core has dedicated hstl i/o buffers which require an addi- tional 1.5v supply known as vddh. the hstl input buffers uses an external reference voltage. the reference volt- age connects to the refi_[1:4] pins. the refi pins should ideally be connected to a noise immune source that is exactly 1/2 the value of the vddh supply. table 78. embedded core power supplies fpga supplies v dd 15 vdd33 vdd33_fpgapll vddio0 vddio1 vddio5 vddio6 vddio7 supply description name serdes input buffers (1.5/1.8v) vddib_a vddib_b vddib_c vddib_d serdes guardband (1.5v) vddgb serdes output buffers (1.5/1.8v) vddob_a vddob_b vddob_c vddob_d serdes analog (1.5v) vdd_ana spi (1.5v) vdda_spia vdda_spib vdda_spic vdda_spid memory controller pll (3.3v) vdda_pll hstl input buffer reference voltage (vddh/2) refi_1 refi_2 refi_3 refi_4 hstl output buffer supply (1.5v) vddh lattice semiconductor orca orspi4 data sheet 194 1036-pin ftsbga devices have been discontinued. recommended power supply connections ideally, a board should have the power supplies described below: vdd33, vdd33_fpgapll and vddio supplies for the fpga logic a single 1.5 v source to supply power to fpga and core digital logic. (vdd15) a dedicated 1.5 v power supply for the serdes analog power pins. this will allow the end user to minimize noise. the guard band pins can also be sourced from the analog power supplies. (vdd_ana, vddgb) serdes tx output buffer power. the power supplies to the serdes tx output buffers should be isolated from the rest of the board power supplies. special care must be taken to minimize noise when providing board level power to these output buffers. the power supply can be 1.5 v or 1.8 v depending on the end application. (vddob) serdes rx input buffer power. the power supplies to the serdes rx input buffers should be isolated from the rest of the board power supplies. special care must be taken to minimize noise when providing board level power to these input buffers. the power supply can be 1.5 v or 1.8 v depending on the end application. (vddib) an isolated 1.5v supply for the vdda_spi to minimize noise from the common 1.5v board supply. (vdd_spi[a:d]) the memory controller bus requires a dedicated 1.5v supply connected to the vddh pins for hstl output buffer supply voltage. (vddh) the hstl input buffers of the memory controller require a voltage reference connected to the refi pins which is half the vddh supply. this supply should be ?tered, and should not exceed a peak-to-peak ac noise of 2% of the vref (dc). the hstl buffer scheme also requires a termination resistor per signal. it is recommended that the clock pin termination be ?tered separately from the data/control pin termination to minimize noise. the vdda_pll supply pin requires a noise minimized 3.3v supply. recommended power supply filtering scheme the board connections of the various serdes v dd and v ss pins are critical to system performance. an example demonstration board schematic is available at www .latticesemi.com . power supply ?tering is in the form of: a parallel bypass capacitor network consisting of 10 ?, 0.1 ?, and 1.0 ? caps close to the power source. a parallel bypass capacitor network consisting of 0.01 ? and 0.1 ? close to the pin. the decoupling capacitor sizes are important as is the employment of various styles of capacitors. this provides frequency response coverage across a greater frequency bandwidth. general decoupling guidelines can be found in lattice semiconductor application note tn1068. example connections are shown in figure 101. the naming convention for the power supply sources shown in the ?ure are as follows: supply_1.5 v ?all digital, auxiliary power pins. supply_v dd ib ?input rx buffer power pins for serdes. supply_v dd ob ?output tx buffer power pins for serdes. supply_v dd ana ?tx analog power pins, rx analog power pins, guard band power pins for serdes. supply_v dd 33, v dd a_pll - fpga and embedded pll power pins. supply v dd a_spia, v dd a_spib, v dd a_spic, v dd a_spid - analog core 1.5v spi supplies. supply v dd h - hstl output buffer power supply of the qdr memory controller. supply refi_1, refi_2, refi_3, refi_4 - voltage reference for hstl input buffer of the qdr memory controller should be one-half vddh lattice semiconductor orca orspi4 data sheet 195 1036-pin ftsbga devices have been discontinued. figure 101. power supply filtering 0.1 f 10 f v dd 15 supply_1.5 v source pin supply_v dd analog v dd ib supply_v dd ib v dd ob supply_v dd ob ? network for every 2 pins ? network for every 2 pins ? each for v dd gb_[a,b] ? network for every 2 pins ? network for every 2 pins 1 f 0.01 f 0.1 f 0.1 f 10 f 1 f 0.01 f 0.1 f v dd _ana 0.1 f 10 f 1 f 0.01 f 0.1 f 0.1 f 10 f 1 f 0.01 f 0.1 f 0.1 f 10 f v dd h supply_1.5 v pin ? network for every 2 pins 1 f 0.01 f 0.1 f 4.7 h 4.7 h 4.7 h 4.7 h 4.7 h lattice semiconductor orca orspi4 data sheet 196 1036-pin ftsbga devices have been discontinued. power supply filtering (continued) 0.1 f 10 f v dd a_spi supply_1.5 v source pin supply_3.3 v vdd33_fpgapll supply_3.3 v refi[1:4] v dd h ? network for every 2 pins ? network for every 2 pins ? network for every 2 pins ? network for refi_1 1 f 0.01 f 0.1 f 0.1 f 10 f 1 f 0.01 f 0.1 f v dd a_pll 0.1 f 10 f 1 f 0.01 f 0.1 f 0.01 f 0.1 f 1k precision 1k precision 1 h refi_2 refi_3 refi_4 4.7 h 4.7 h 4.7 h lattice semiconductor orca orspi4 data sheet 197 1036-pin ftsbga devices have been discontinued. pin descriptions this section describes the pins found on the series 4 fpgas. any pin not described in this table is a user-program- mable i/o. during con?uration, the user-programmable i/os are 3-stated with an internal pull-up resistor. if any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor after con?uration. the pin descriptions in table and throughout this data sheet show active-low signals with an overscore. the pack- age pinout tables that follow, show this as a signal ending with _n. for example ldc and ldc_n are equivalent. table 79. pin descriptions symbol i/o description dedicated pins v dd 33 3.3v positive power supply. this power supply is used for 3.3 v con?uration rams. vdd33_fpgapll 3.3v positive power supply. this power supply is used for 3.3 v internal plls. this power sup- ply should be well isolated from all other power supplies on the board for proper operation. v dd 15 1.5 v positive power supply for internal logic. v dd io positive power supply used by i/o banks. v ss ground. ptemp i temperature sensing diode pin. dedicated input. reset i during con?uration, reset forces the restart of con?uration and a pull-up is enabled. after con?uration, reset can be used as a general fpga input or as a direct input, which causes all plc latches/ffs to be asynchronously set/reset. cclk o in the master and asynchronous peripheral modes, cclk is an output which strobes con?ura- tion data in. i in the slave or readback after con?uration, cclk is input synchronous with the data on din or d[7:0]. cclk is an output for daisy-chain operation when the lead device is in master, periph- eral, or system bus modes. done i as an input, a low level on done delays fpga start-up after con?uration. 1 o as an active-high, open-drain output, a high level on this signal indicates that con?uration is complete. done has an optional pull-up resistor. prgrm i prgrm is an active-low input that forces the restart of con?uration and resets the boundary- scan circuitry. this pin always has an active pull-up. rd_cfg i this pin must be held high during device initialization until the init pin goes high. this pin always has an active pull-up. during con?uration, rd_cfg is an active-low input that activates the ts_all function and 3-states all of the i/o. after con?uration , rd_cfg can be selected (via a bit stream option) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on rd_cfg will initiate readback of the con?uration data, including pfu output states, starting with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides con?uration data out. if used in boundary-scan, tdo is test data out. cfg_irq /mpi_irq o during jtag, slave, master, and asynchronous peripheral con?uration assertion on this cfg_irq (active-low) indicates an error or errors for block ram or fpsc initialization. mpi active-low interrupt request output, when the mpi is used. lvds_r - reference resistor connection for controlled impedance termination of series 4 fpga lvds inputs. special-purpose pins m[3:0] i during power up and initialization, m0?3 are used to select the con?uration mode with their values latched on the rising edge of init . during con?uration, a pull-up is enabled. i/o after con?uration, these pins are user-programmable i/o. 1 pll_ck[0:7][tc] i semi-dedicated pll clock pins. during con?uration they are 3-stated with a pull up. i/o these pins are user-programmable i/o pins if not used by plls after con?uration. p[tblr]clk[1:0][tc] i pins dedicated for the primary clock. input pins on the middle of each side with differential pair- ing. i/o after con?uration these pins are user programmable i/o, if not used for clock inputs. lattice semiconductor orca orspi4 data sheet 198 1036-pin ftsbga devices have been discontinued. tdi, tck, tms i if boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. if boundary-scan is not selected, all boundary-scan functions are inhibited once con?uration is complete. even if boundary-scan is not used, either tck or tms must be held at logic 1 during con?uration. each pin has a pull-up enabled during con?uration. i/o after con?uration, these pins are user-programmable i/o if boundary scan is not used. 1 rdy/b usy /rclk o during con?uration in asynchronous peripheral mode, rdy/rclk indicates another byte can be written to the fpga. if a read operation is done when the device is selected, the same sta- tus is also available on d7 in asynchronous peripheral mode. during the master parallel con?uration mode, rclk is a read output signal to an external memory. this output is not normally used. i/o after con?uration this pin is a user-programmable i/o pin. 1 hdc o high during con?uration is output high until con?uration is complete. it is used as a control output, indicating that con?uration is not complete. i/o after con?uration, this pin is a user-programmable i/o pin. 1 ldc o lo w dur ing con gur ation is output low until con?uration is complete. it is used as a control out- put, indicating that con?uration is not complete. i/o after con?uration, this pin is a user-programmable i/o pin. 1 init i/o init is a bidirectional signal before and during con?uration. during con?uration, a pull-up is enabled, but an external pull-up resistor is recommended. as an active-low open-drain output, init is held low during power stabilization and internal clearing of memory. as an active-low input, init holds the fpga in the wait-state before the start of con?uration. after con?uration, this pin is a user-programmable i/o pin. 1 cs0 , cs1 i cs0 and cs1 are used in the asynchronous peripheral, slave parallel, and microprocessor con- ?uration modes. the fpga is selected when cs0 is low and cs1 is high. during con?ura- tion, a pull-up is enabled. i/o after con?uration, if mpi is not used, these pins are user-programmable i/o pins. 1 rd /mpi_strb i rd is used in the asynchronous peripheral con?uration mode. a low on rd changes d[7:3] into a status output. wr and rd should not be used simultaneously. if they are, the write strobe overrides. this pin is also used as the mpi data transfer strobe. as a status indication, a high indicates ready, and a low indicates busy. wr /mpi_rw i wr is used in asynchronous peripheral mode. a low on wr transfers data on d[7:0] to the fpga. in mpi mode, a high on mpi_rw allows a read from the data bus, while a low causes a write transfer to the fpga. i/o after con?uration, if the mpi is not used, wr /mpi_rw is a user-programmable i/o pin. 1 ppc_a[14:31] i during mpi mode the ppc_a[14:31] are used as the address bus driven by the powerpc bus master utilizing the least-signi?ant bits of the powerpc 32-bit address. mpi_b urst i mpi_b urst is driven low to indicate a burst transfer is in progress in mpi mode. driven high indicates that the current transfer is not a burst. mpi_bdip i mpi_bdip is driven by the powerpc processor in mpi mode. assertion of this pin indicates that the second beat in front of the current one is requested by the master. negated before the burst transfer ends to abort the burst data phase. mpi_tsz[0:1] i mpi_tsz[0:1] signals are driven by the bus master in mpi mode to indicate the data transfer size for the transaction. set 01 for byte, 10 for half-word, and 00 for word. a[21:0] o during master parallel mode a[21:0] address the con?uration eproms up to 4m bytes. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 mpi_ack o in mpi mode this is driven low indicating the mpi received the data on the write cycle or returned data on a read cycle. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 table 79. pin descriptions (continued) symbol i/o description lattice semiconductor orca orspi4 data sheet 199 1036-pin ftsbga devices have been discontinued. mpi_clk i this is the powerpc synchronous, positive-edge bus clock used for the mpi interface. it can be a source of the clock for the embedded system bus. if mpi is used this will be the amba bus clock. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 mpi_tea o a low on the mpi transfer error acknowledge indicates that the mpi detects a bus error on the internal system bus for the current transaction. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 mpi_rtry o this pin requests the mpc860 to relinquish the bus and retry the cycle. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 d[0:31] i/o selectable data bu s width from 8, 16, 32-bit in mpi mode. driven by the bus master in a write transaction and driven by mpi in a read transaction. i d[7:0] receive con?uration data during master parallel, peripheral, and slave parallel con?u- ration modes when wr is low and each pin has a pull-up enabled. during serial con?uration modes, d0 is the din input. o d[7:3] output internal status for asynchronous peripheral mode when rd is low. i/o after con?uration, if mpi is not used, the pins are user-programmable i/o pins. 1 dp[0:3] i/o selectable parity bus width in mpi mode from 1, 2, 4-bit, dp[0] for d[0:7], dp[1] for d[8:15], dp[2] for d[16:23], and dp[3] for d[24:31]. after con?uration, if mpi is not used, the pins are user-programmable i/o pin. 1 din i during slave serial or master serial con?uration modes, din accepts serial con?uration data synchronous with cclk. during parallel con?uration modes, din is the d0 input. during con- ?uration, a pull-up is enabled. i/o after con?uration, this pin is a user-programmable i/o pin. 1 dout o during con?uration, dout is the serial data output that can drive the din of daisy-chained slave devices. data out on dout changes on the rising edge of cclk. i/o after con?uration, dout is a user-programmable i/o pin. 1 testcfg i during con?uration this pin should be held high, to allow con?uration to occur. a pull up is enabled during con?uration. i/o after con?uration, testcfg is a user programmable i/o pin. 1 1. the fpga states of operation section in the orca series 4 fpgas data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con?uration pins (and the activation of all user i/os) is controlled by a second set of options. table 79. pin descriptions (continued) symbol i/o description lattice semiconductor orca orspi4 data sheet 200 1036-pin ftsbga devices have been discontinued. orspi4 spi4 external i/o description this section describes device i/o signals to/from the spi4 interface. table 80 and table 81 lists the external signals that interface to the spi4 block. table 80. spi4 external transmit path interface signals table 81. spi4 external receive path interface signals pin name (j = a or b) direction o = fpsc output i = fpsc input description tsclkj i lvttl transmit status clock input. tstatj[1:0] i lvttl transmit status input jtsclkn i lvds (negative) transmit status clock input jtsclkp i lvds (positive) transmit status clock input jtstatn[1:0] i lvds (negative) transmit status data input jtstatp[1:0] i lvds (positive) transmit status data input jtdatn[15:0] o lvds (negative) transmit spi4 data output jtdatp[15:0] o lvds (positive) transmit spi4 data output jtctln o lvds (negative) transmit spi4 control signal output jtctlp o lvds (positive) transmit spi4 control signal output jtdclkn o lvds (negative) transmit spi4 clock reference. (100 - > 450 mhz) jtdclkp o lvds (positive) transmit spi4 clock reference. (100 - >450 mhz) jtrefclk i spi4 clock reference input. pin name (j = a or b) direction o = fpsc output i = fpsc input description rsclkj o lvttl receive status clock output. rstatj[1:0] o lvttl receive status output jrsclkn o lvds (negative) receive status clock output jrsclkp] o lvds (positive) receive status clock output jrstatn[1:0] o lvds (negative) receive status data output jrstatp[1:0 o lvds (positive) receive status data output jrdatn[15:0] i lvds (negative) receive spi4 data input jrdatp[15:0] i lvds (positive) receive spi4 data input jrctln i lvds (negative) receive spi4 control signal input jrctlp i lvds (positive) receive spi4 control signal input jrdclkn i lvds (negative) receive spi4 clock reference. (100 - >450 mhz) jrdclkp i lvds (positive) receive spi4 clock reference. (100 - >450 mhz) lattice semiconductor orca orspi4 data sheet 201 1036-pin ftsbga devices have been discontinued. table 82. spi4 miscellaneous system signals pin name (j = a or b) direction o = fpsc output i = fpsc input description ref10 i lvds reference voltage: 1.0 v +/- 3% ref14 i lvds reference voltage: 1.4 v +/- 3% reshi i lvds resistor high pin (100 . in series with reslo) reslo i lvds resistor low pin (100 . in series with reshi) alvctap1 i/o lvds input center tap (use 0.01 f to gnd) alvctap2 i/o lvds input center tap (use 0.01 f to gnd) alvctap3 i/o lvds input center tap (use 0.01 f to gnd) alvctap4 i/o lvds input center tap (use 0.01 f to gnd) alvctap5 i/o lvds input center tap (use 0.01 f to gnd) blvctap1 i/o lvds input center tap (use 0.01 f to gnd) blvctap2 i/o lvds input center tap (use 0.01 f to gnd) blvctap3 i/o lvds input center tap (use 0.01 f to gnd) blvctap4 i/o lvds input center tap (use 0.01 f to gnd) blvctap5 i/o lvds input center tap (use 0.01 f to gnd) spare_1 i/o reserved spare_2 i/o reserved lattice semiconductor orca orspi4 data sheet 202 1036-pin ftsbga devices have been discontinued. orspi4 serdes external i/o description this section describes device i/o signals to/from the serdes. table 83 lists the external signals that interface to the serdes block. table 83. serdes external interface signals pin name direction o = fpsc output i = fpsc input description serdes interface pins hdinp_a i serial input for channel a hdinn_a hdinp_b i serial input for channel b hdinn_b hdinp_c i serial input for channel c hdinn_c hdinp_d i serial input for channel d hdinn_d hdoutp_a o serial output for channel a hdoutn_a hdoutp_b o serial output for channel b hdoutn_b hdoutp_c o serial output for channel c hdoutn_c hdoutp_d o serial output for channel d hdoutn_d refclkp i reference clock to serdes quad refclkn rext -- reference resistor rextn -- reference resistor. a 3.32 kw ?1% resistor must be connected across rext and rextn. this current should handle a total of 300 a. misc system signals resetn i global reset integrated 50k pull-down allows chip to stay in reset state when external driver loses power testmd[1:0]n i lvttl test mode pins with integrated 50k pull-ups that default chip into operational mode when un-driven. pdn i power-down active low. puts core into low-power (non-func- tional) state. tristn i active low control input causes all output pins to be disabled. (see note 1) testclk i chip test pin. integrated 50k pull-up 1. should be externally connected on board to 3.3 v pullup resistor. lattice semiconductor orca orspi4 data sheet 203 1036-pin ftsbga devices have been discontinued. orspi4 memory controller external i/o description this section describes device i/o signals to/from the memory controller. table 84 lists the external signals that interface to the memory controller block. table 84. memory controller external interface signals pin name qdrii sdram pin name direction o = fpsc output i = fpsc input description interface to qdrii sdram pmik, pmikn k,k# o clock for write data d, address sa, and enables w# and r# pmid(35:0) d(35:0) o write data bus pmia(17:0) sa(17:0) o address bus pmiwn w# o write enable (active-lo) pmirn r# o read enable (active-lo) pmic, pmicn cq,cq# i clock for read data q pmiq(35:0) q(35:0) i read data bus refclk source inputs mcrefclk - i dedicated memory controller reference clock (hstl) atrefclk -i spia reference clock (lvttl). note that this signal also is fed to the spia block. btrefclk -i spib reference clock, (lvttl). note that this signal also is fed to the spib block. other signals ext_1k -- reference resistor. connect to a 1.5 k ?1% precision resistor to ground. this current should handle a total of 700 a. lattice semiconductor orca orspi4 data sheet 204 1036-pin ftsbga devices have been discontinued. package i/o table 85. i/o summary package i/o type fte1036 f1156/fn1156 user programmable i/o 498 356 available programmable differential pair pins 498 356 fpga con?uration pins 7 7 fpga dedicated function pins 2 2 core function pins 322 301 vdd15 42 80 vdd33 14 30 vdd33_fpgapll 8 8 vddio 30 50 vss 79 187 vddgb 1 0 vddib 4 0 vddob 8 0 vdd_ana 4 0 vdda_spi[a:d] 4 4 vdda_pll 1 1 vddh 8 30 hstl vref 4 4 no connect 0 96 total package pins 1036 1156 lattice semiconductor orca orspi4 data sheet 205 1036-pin ftsbga devices have been discontinued. pin tables the orspi4 fpsc is available in two package types; a 1156-pin fpbga package, and a 1036-pin ftsbga pack- age. both packages are 1.0 mm pitch packages. the 1036-pin package offers two spi4 interfaces, or one spi4 interface and a quad 0.6-3.7 gbps serdes, a high- speed qdr-ii sram memory controller, and 498 user i/os on the fpga array. the 1156-pin package offers two spi4 interfaces (no serdes available on this package offering), a high-speed qdr-ii sram memory controller, and 356 user i/os on the fpga array. table 86. 1156 fpbga pin table f1156 ball vddio bank vref group i/o pin description additional function f1156 pair f4 - - o prd_data rd_data/tdo - g4 - - i preset_n reset_n - h4 - - i prd_cfg_n rd_cfg_n - j4 - - i pprgrm_n prgrm_n - h5 0 (tl) 7 io pl2d pll_ck0c/hppll l1c h6 0 (tl) 7 io pl2c pll_ck0t/hppll l1t j6 0 (tl) 7 io pl3d - l2c j5 0 (tl) 7 io pl3c vref_0_07 l2t h3 0 (tl) 7 io pl4d d5 l3c j3 0 (tl) 7 io pl4c d6 l3t k4 0 (tl) 8 io pl5d - l4c k5 0 (tl) 8 io pl5c vref_0_08 l4t g2 0 (tl) 8 io pl6d hdc l5c g1 0 (tl) 8 io pl6c ldc_n l5t l5 0 (tl) 8 io pl7d - l6c l4 0 (tl) 8 io pl7c - l6t h2 0 (tl) 9 io pl8d testcfg l7c h1 0 (tl) 9 io pl8c d7 l7t j2 0 (tl) 9 io pl9d vref_0_09 l8c j1 0 (tl) 9 io pl9c a17/ppc_a31 l8t k2 0 (tl) 9 io pl10d cs0_n l9c k1 0 (tl) 9 io pl10c cs1 l9t k3 0 (tl) 10 io pl11d - l10c l3 0 (tl) 10 io pl11c - l10t l2 0 (tl) 10 io pl12d init_n l11c l1 0 (tl) 10 io pl12c dout l11t m4 0 (tl) 10 io pl13d vref_0_10 l12c m5 0 (tl) 10 io pl13c a16/ppc_a30 l12t n5 7 (cl) 1 io pl14d a15/ppc_a29 l13c n4 7 (cl) 1 io pl14c a14/ppc_a28 l13t m3 7 (cl) 1 io pl15d - l14c n3 7 (cl) 1 io pl15c - l14t p4 7 (cl) 1 io pl16d vref_7_01 l15c lattice semiconductor orca orspi4 data sheet 206 1036-pin ftsbga devices have been discontinued. p3 7 (cl) 1 io pl16c d4 l15t m2 7 (cl) 2 io pl17d - l16c m1 7 (cl) 2 io pl17c - l16t n2 7 (cl) 2 io pl18d rdy/busy_n/rclk l17c n1 7 (cl) 2 io pl18c vref_7_02 l17t p5 7 (cl) 2 io pl19d a13/ppc_a27 l18c r5 7 (cl) 2 io pl19c a12/ppc_a26 l18t r4 7 (cl) 3 io pl20d - l19c r3 7 (cl) 3 io pl20c - l19t p2 7 (cl) 3 io pl21d a11/ppc_a25 l20c p1 7 (cl) 3 io pl21c vref_7_03 l20t t3 7 (cl) 3 io pl22d - l21c t4 7 (cl) 3 io pl22c - l21t r1 7 (cl) 4 io pl23d rd_n/mpi_strb_ n l22c r2 7 (cl) 4 io pl23c vref_7_04 l22t r6 7 (cl) 4 io pl24d plck0c l23c t6 7 (cl) 4 io pl24b - l178c t5 7 (cl) 4 io pl24c plck0t l23t u5 7 (cl) 4 io pl24a - l178t u3 7 (cl) 5 io pl25d a10/ppc_a24 l24c u4 7 (cl) 5 io pl25c a9/ppc_a23 l24t t1 7 (cl) 5 io pl26d a8/ppc_a22 l25c t2 7 (cl) 5 io pl26c vref_7_05 l25t v3 7 (cl) 5 io pl27d - l26c v4 7 (cl) 5 io pl27c - l26t u1 7 (cl) 6 io pl28d plck1c l27c u2 7 (cl) 6 io pl28c plck1t l27t v5 7 (cl) 6 io pl29d vref_7_06 l28c w5 7 (cl) 6 io pl29c a7/ppc_a21 l28t w3 7 (cl) 6 io pl30d a6/ppc_a20 l29c w4 7 (cl) 6 io pl30c a5/ppc_a19 l29t v1 7 (cl) 7 io pl31d - l30c v2 7 (cl) 7 io pl31c - l30t w1 7 (cl) 7 io pl32d wr_n/mpi_rw l31c w2 7 (cl) 7 io pl32c vref_7_07 l31t y1 7 (cl) 7 io pl33d - l32c y2 7 (cl) 7 io pl33c - l32t aa1 7 (cl) 8 io pl34d a4/ppc_a18 l33c aa2 7 (cl) 8 io pl34c vref_7_08 l33t y3 7 (cl) 8 io pl35d a3/ppc_a17 l34c w6 7 (cl) 8 io pl35b - l35c aa3 7 (cl) 8 io pl35c a2/ppc_a16 l34t table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 207 1036-pin ftsbga devices have been discontinued. y6 7 (cl) 8 io pl35a - l35t ab1 7 (cl) 8 io pl36d a1/ppc_a15 l36c y5 7 (cl) 8 io pl36b - l37c ab2 7 (cl) 8 io pl36c a0/ppc_a14 l36t y4 7 (cl) 8 io pl36a - l37t ac1 7 (cl) 8 io pl37d dp0 l38c aa5 7 (cl) 8 io pl37b - l39c ac2 7 (cl) 8 io pl37c dp1 l38t aa4 7 (cl) 8 io pl37a - l39t ad1 6 (bl) 1 io pl38d d8 l40c aa6 6 (bl) 1 io pl38b - l41c ad2 6 (bl) 1 io pl38c vref_6_01 l40t ab6 6 (bl) 1 io pl38a - l41t ab3 6 (bl) 1 io pl39d d9 l42c ab4 6 (bl) 1 io pl39b - l43c ac3 6 (bl) 1 io pl39c d10 l42t ab5 6 (bl) 1 io pl39a - l43t ae1 6 (bl) 2 io pl40d - l44c ac4 6 (bl) 2 io pl40b - l45c ae2 6 (bl) 2 io pl40c vref_6_02 l44t ac5 6 (bl) 2 io pl40a - l45t af1 6 (bl) 2 io pl41d - l46c ad5 6 (bl) 2 io pl41b - l47c af2 6 (bl) 2 io pl41c - l46t ad4 6 (bl) 2 io pl41a - l47t ad3 6 (bl) 3 io pl42d d11 l48c ae4 6 (bl) 3 io pl42b - l49c ae3 6 (bl) 3 io pl42c d12 l48t ae5 6 (bl) 3 io pl42a - l49t ag1 6 (bl) 3 io pl43d - l50c af4 6 (bl) 3 io pl43b - l51c ag2 6 (bl) 3 io pl43c - l50t af5 6 (bl) 3 io pl43a - l51t ah1 6 (bl) 3 io pl44d vref_6_03 l52c ac6 6 (bl) 4 io pl44b - l53c ah2 6 (bl) 3 io pl44c d13 l52t ad6 6 (bl) 4 io pl44a - l53t af3 6 (bl) 4 io pl45d - l54c ae6 6 (bl) 4 io pl45b - l55c ag3 6 (bl) 4 io pl45c vref_6_04 l54t af6 6 (bl) 4 io pl45a - l55t aj1 6 (bl) 4 io pl46d - l56c aj2 6 (bl) 4 io pl46c - l56t table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 208 1036-pin ftsbga devices have been discontinued. ah3 6 (bl) 4 io pl47d pll_ck7c/hppll l57c aj3 6 (bl) 4 io pl47c pll_ck7t/hppll l57t ag4 - - i ptemp ptemp - ah4 - - io lvds_r lvds_r - ah6 6 (bl) 5 io pb2a dp2 l58t an5 6 (bl) 5 io pb2c pll_ck6t/ppll l59t ah7 6 (bl) 5 io pb2b - l58c ap5 6 (bl) 5 io pb2d pll_ck6c/ppll l59c an6 6 (bl) 5 io pb3c - l60t ap6 6 (bl) 5 io pb3d - l60c ak6 6 (bl) 5 io pb4c vref_6_05 l61t ak7 6 (bl) 5 io pb4d dp3 l61c aj6 6 (bl) 6 io pb5a - l62t al6 6 (bl) 6 io pb5c - l63t aj7 6 (bl) 6 io pb5b - l62c al7 6 (bl) 6 io pb5d - l63c ag7 6 (bl) 6 io pb6a - l64t am6 6 (bl) 6 io pb6c vref_6_06 l65t ag8 6 (bl) 6 io pb6b - l64c am7 6 (bl) 6 io pb6d d14 l65c ag9 6 (bl) 6 io pb7a - l66t an7 6 (bl) 6 io pb7c - l67t ag10 6 (bl) 6 io pb7b - l66c ap7 6 (bl) 6 io pb7d - l67c ah8 6 (bl) 7 io pb8a - l68t an8 6 (bl) 7 io pb8c d15 l69t aj8 6 (bl) 7 io pb8b - l68c ap8 6 (bl) 7 io pb8d d16 l69c ah9 6 (bl) 7 io pb9a - l70t ak8 6 (bl) 7 io pb9c d17 l71t aj9 6 (bl) 7 io pb9b - l70c ak9 6 (bl) 7 io pb9d d18 l71c aj10 6 (bl) 7 io pb10a - l72t al8 6 (bl) 7 io pb10c vref_6_07 l73t ah10 6 (bl) 7 io pb10b - l72c al9 6 (bl) 7 io pb10d d19 l73c am8 6 (bl) 8 io pb11c d20 l74t am9 6 (bl) 8 io pb11d d21 l74c aj11 6 (bl) 8 io pb12a - l75t an9 6 (bl) 8 io pb12c vref_6_08 l76t ah11 6 (bl) 8 io pb12b - l75c ap9 6 (bl) 8 io pb12d d22 l76c ag11 6 (bl) 9 io pb13a - l77t table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 209 1036-pin ftsbga devices have been discontinued. ak10 6 (bl) 9 io pb13c d23 l78t ag12 6 (bl) 9 io pb13b - l77c ak11 6 (bl) 9 io pb13d d24 l78c aj12 6 (bl) 9 io pb14a - l79t an10 6 (bl) 9 io pb14c vref_6_09 l80t ah12 6 (bl) 9 io pb14b - l79c ap10 6 (bl) 9 io pb14d d25 l80c aj13 6 (bl) 9 io pb15a - l81t al10 6 (bl) 9 io pb15c - l82t ah13 6 (bl) 9 io pb15b - l81c al11 6 (bl) 9 io pb15d - l82c aj14 6 (bl) 10 io pb16a - l83t am10 6 (bl) 10 io pb16c d26 l84t ah14 6 (bl) 10 io pb16b - l83c am11 6 (bl) 10 io pb16d d27 l84c aj16 6 (bl) 10 io pb17a - l85t an11 6 (bl) 10 io pb17c - l86t ah16 6 (bl) 10 io pb17b - l85c ap11 6 (bl) 10 io pb17d - l86c aj17 6 (bl) 10 io pb18a - l87t ak12 6 (bl) 10 io pb18c vref_6_10 l88t ah17 6 (bl) 10 io pb18b - l87c ak13 6 (bl) 10 io pb18d d28 l88c ag13 6 (bl) 11 io pb19a - l89t an12 6 (bl) 11 io pb19c d29 l90t ag14 6 (bl) 11 io pb19b - l89c ap12 6 (bl) 11 io pb19d d30 l90c ah15 6 (bl) 11 io pb20a - l91t al12 6 (bl) 11 io pb20c vref_6_11 l92t aj15 6 (bl) 11 io pb20b - l91c al13 6 (bl) 11 io pb20d d31 l92c aj18 5 (bc) 1 io pb21a - l93t am12 5 (bc) 1 io pb21c - l94t ah18 5 (bc) 1 io pb21b - l93c am13 5 (bc) 1 io pb21d - l94c aj19 5 (bc) 1 io pb22a - l95t an13 5 (bc) 1 io pb22c vref_5_01 l96t ah19 5 (bc) 1 io pb22b - l95c ap13 5 (bc) 1 io pb22d - l96c ap14 5 (bc) 2 io pb23c pbck0t l97t an14 5 (bc) 2 io pb23d pbck0c l97c ag15 5 (bc) 2 io pb24a - l99t ak14 5 (bc) 2 io pb24c vref_5_02 l98t table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 210 1036-pin ftsbga devices have been discontinued. ag16 5 (bc) 2 io pb24b - l99c ak15 5 (bc) 2 io pb24d - l98c al14 5 (bc) 2 io pb25c - l100t al15 5 (bc) 2 io pb25d - l100c am14 5 (bc) 3 io pb26c - l101t am15 5 (bc) 3 io pb26d vref_5_03 l101c ag18 5 (bc) 3 io pb27a - l102t an15 5 (bc) 3 io pb27c - l103t ag17 5 (bc) 3 io pb27b - l102c ap15 5 (bc) 3 io pb27d - l103c al16 5 (bc) 3 io pb28c pbck1t l104t am16 5 (bc) 3 io pb28d pbck1c l104c an16 5 (bc) 4 io pb29c - l105t ap16 5 (bc) 4 io pb29d - l105c ak16 5 (bc) 4 io pb30c - l106t ak17 5 (bc) 4 io pb30d vref_5_04 l106c an17 5 (bc) 4 io pb31c - l107t ap17 5 (bc) 4 io pb31d - l107c al17 5 (bc) 5 io pb32c - l108t am17 5 (bc) 5 io pb32d vref_5_05 l108c ak18 5 (bc) 5 io pb33c - l109t al18 5 (bc) 5 io pb33d - l109c an18 5 (bc) 5 io pb34c - l110t ap18 5 (bc) 5 io pb34d - l110c an19 5 (bc) 6 io pb35c - l111t ap19 5 (bc) 6 io pb35d vref_5_06 l111c am18 5 (bc) 6 io pb36c - l112t am19 5 (bc) 6 io pb36d - l112c an20 5 (bc) 7 io pb37c - l113t ap20 5 (bc) 7 io pb37d - l113c al19 5 (bc) 7 io pb38c vref_5_07 l114t al20 5 (bc) 7 io pb38d - l114c ak19 5 (bc) 7 io pb39c - l115t ak20 5 (bc) 7 io pb39d - l115c am20 5 (bc) 8 io pb40c - l116t am21 5 (bc) 8 io pb40d vref_5_08 l116c an21 5 (bc) 8 io pb41c - l117t ap21 5 (bc) 8 io pb41d - l117c an22 5 (bc) 8 io pb42c - l118t ap22 5 (bc) 8 io pb42d - l118c al21 5 (bc) 9 io pb43c - l119t al22 5 (bc) 9 io pb43d - l119c ak21 5 (bc) 9 io pb44c - l120t table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 211 1036-pin ftsbga devices have been discontinued. ak22 5 (bc) 9 io pb44d vref_5_09 l120c am22 5 (bc) 9 io pb45c - l121t am23 5 (bc) 9 io pb45d - l121c an23 5 (bc) 10 io pb46c - l122t ap23 5 (bc) 10 io pb46d vref_5_10 l122c al23 - - i resetn - - ak23 - - i tristn - - ap24 - - i testmd1n - - an24 - - i testmd0n - - am24 - - i pdn - - al24 - - i atrefclk - - ak24 - - i testclk - - ap25 - - i btrefclk - - an25 - - i tstat1b - - ag22 - - i tstat0b - - am25 - - i tsclkb - - ah23 - - o rstat1b - - al25 - - o rstat0b - - ah24 - - o rsclkb - - ak30 - - i atstat1n - r1c al31 - - i atstat0n - r2c aj30 - - i atstat1p - r1t ak31 - - i atstat0p - r2t am31 - - i atsclkn - r3c ae27 - - i/o alvctap5 - - al32 - - i atsclkp - r3t af29 - - i btsclkn - r4c ah30 - - i/o blvctap5 - - ag28 - - i btsclkp - r4t am32 - - i btstat1n - r5c af28 - - i btstat0n - r6c am33 - - i btstat1p - r5t ae28 - - i btstat0p - r6t ak32 - - o brstat1n - r7c al33 - - o brstat0n - r8c aj32 - - o brstat1p - r7t al34 - - o brstat0p - r8t aj31 - - o brsclkn - r9c ae26 - - o arsclkn - r10c ah31 - - o brsclkp - r9t ad26 - - o arsclkp - r10t ak33 - - o arstat1n - r11c aj33 - - o arstat0n - r12c table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 212 1036-pin ftsbga devices have been discontinued. ak34 - - o arstat1p - r11t aj34 - - o arstat0p - r12t af31 - - i reslo - - ad28 - - i reshi - - ag31 - - i ref14 - - ae29 - - i ref10 - - ah32 - - o btdat15n - r13c ag29 - - o btdat14n - r14c ag32 - - o btdat15p - r13t ag30 - - o btdat14p - r14t ah33 - - o btdat13n - r15c ad27 - - o btdat12n - r16c ah34 - - o btdat13p - r15t ac27 - - o btdat12p - r16t ag33 - - o btdat11n - r17c ae30 - - o btdat10n - r18c ag34 - - o btdat11p - r17t af30 - - o btdat10p - r18t af32 - - o btdat9n - r19c ad30 - - o btdat8n - r20c ae32 - - o btdat9p - r19t ad29 - - o btdat8p - r20t af33 - - o btctln - r21c ab26 - - o btdclkn - r22c af34 - - o btctlp - r21t ac26 - - o btdclkp - r22t ae31 - - vdda_spia vdda_spia - - ad31 - - vss vss - - ac28 - - o btdat7n - r23c ae33 - - o btdat6n - r24c ac29 - - o btdat7p - r23t ae34 - - o btdat6p - r24t ad32 - - o btdat5n - r25c ab28 - - o btdat4n - r26c ac32 - - o btdat5p - r25t ab29 - - o btdat4p - r26t ad33 - - o btdat3n - r27c ac30 - - o btdat2n - r28c ad34 - - o btdat3p - r27t ab30 - - o btdat2p - r28t ac31 - - o btdat1n - r29c ab27 - - o btdat0n - r30c ab31 - - o btdat1p - r29t table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 213 1036-pin ftsbga devices have been discontinued. aa27 - - o btdat0p - r31t ac33 - - i brdclkn - r32c aa29 - - i brdat15n - r33c ac34 - - i brdclkp - r32t aa30 - - i brdat15p - r33t aa31 - - i/o blvctap1 - - aa26 - - i brdat14n - r34c ab33 - - i brdat13n - r35c y26 - - i brdat14p - r34t ab34 - - i brdat13p - r35t aa28 - - i brdat12n - r36c ab32 - - i brdat11n - r37c y28 - - i brdat12p - r36t aa32 - - i brdat11p - r37t y30 - - i brdat10n - r38c aa33 - - i/o blvctap2 - - y29 - - i brdat10p - r38t y31 - - i brdat9n - r39c y27 - - i brdat8n - r40c y32 - - i brdat9p - r39t w27 - - i brdat8p - r40t aa34 - - i brctln - r41c w28 - - i/o blvctap3 - - y34 - - i brctlp - r41t w30 - - i brdat7n - r42c y33 - - i brdat6n - r43c w29 - - i brdat7p - r42t w33 - - i brdat6p - r43t w26 - - i brdat5n - r44c w31 - - i brdat4n - r45c v26 - - i brdat5p - r44t w32 - - i brdat4p - r45t v28 - - i/o blvctap4 - - w34 - - i brdat3n - r46c v30 - - i brdat2n - r47c v34 - - i brdat3p - r46t v29 - - i brdat2p - r47t v33 - - i brdat1n - r48c v27 - - i brdat0n - r49c v32 - - i brdat1p - r48t u27 - - i brdat0p - r49t v31 - - vss vss - - u31 - - vdda_spib vdda_spib - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 214 1036-pin ftsbga devices have been discontinued. u28 - - o atdat15n - r50c u32 - - vss vss - - u29 - - o atdat15p - r50t u33 - - o atdat14n - r51c u34 - - o atdat14p - r51t u30 - - o atdat13n - r52c t34 - - o atdat12n - r53c t29 - - o atdat13p - r52t t33 - - o atdat12p - r53t t32 - - o atdat11n - r54c u26 - - o atdat10n - r55c t31 - - o atdat11p - r54t t26 - - o atdat10p - r55t r34 - - o atdat9n - r56c t28 - - o atdat8n - r57c r33 - - o atdat9p - r56t t30 - - o atdat8p - r57t r32 - - o atctln - r58c t27 - - o atdclkn - r59c r31 - - o atctlp - r58t r27 - - o atdclkp - r59t p34 - - o atdat7n - r60c r28 - - o atdat6n - r61c p33 - - o atdat7p - r60t r29 - - o atdat6p - r61t n34 - - o atdat5n - r62c r30 - - o atdat4n - r63c n33 - - o atdat5p - r62t p30 - - o atdat4p - r63t p32 - - o atdat3n - r64c r26 - - o atdat2n - r65c p31 - - o atdat3p - r64t p26 - - o atdat2p - r65t m34 - - o atdat1n - r66c p28 - - o atdat0n - r67c m33 - - o atdat1p - r66t p29 - - o atdat0p - r67t n31 - - vss vss - - m32 - - vdda_spic vdda_spic - - n32 - - vss vss - - l34 - - i ardclkn - r68c p27 - - i ardat15n - r69c l33 - - i ardclkp - r68t table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 215 1036-pin ftsbga devices have been discontinued. n27 - - i ardat15p - r69t l32 - - i/o alvctap1 - - n30 - - i ardat14n - r70c k34 - - i ardat13n - r71c m30 - - i ardat14p - r70t k33 - - i ardat13p - r71t n28 - - i ardat12n - r72c j32 - - i ardat11n - r73c n29 - - i ardat12p - r72t k32 - - i ardat11p - r73t l30 - - i/o alvctap2 - - m31 - - i ardat10n - r74c n26 - - i ardat9n - r75c l31 - - i ardat10p - r74t m26 - - i ardat9p - r75t j34 - - i ardat8n - r76c m28 - - i arctln - r77c j33 - - i ardat8p - r76t m29 - - i arctlp - r77t k31 - - i/o alvctap3 - - l27 - - i ardat7n - r78c h34 - - i ardat6n - r79c m27 - - i ardat7p - r78t h33 - - i ardat6p - r79t l29 - - i ardat5n - r80c j31 - - i ardat4n - r81c k30 - - i ardat5p - r80t h31 - - i ardat4p - r81t l28 - - i/o alvctap4 - - g34 - - i ardat3n - r82c j30 - - i ardat2n - r83c g33 - - i ardat3p - r82t h30 - - i ardat2p - r83t f34 - - i ardat1n - r84c l26 - - i ardat0n - r85c f33 - - i ardat1p - r84t k26 - - i ardat0p - r85t h32 - - vdda_spid vdda_spid - - g32 - - vss vss - - g30 - - i tstat1a - - g31 - - i tstat0a - - h29 - - i tsclka - - f32 - - o rstat1a - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 216 1036-pin ftsbga devices have been discontinued. k29 - - o rstat0a - - e34 - - o rsclka - - e33 - - i/o pmia17 - - d34 - - i/o pmia16 - - k28 - - i/o pmia15 - - d33 - - i/o pmia14 - - g29 - - i/o pmia13 - - c33 - - i/o pmia12 - - k27 - - i/o pmia11 - - e32 - - i/o pmia10 - - d32 - - i/o pmia9 - - c32 - - i/o pmia8 - - g28 - - i/o pmiwn - - b32 - - i/o pmirn - - j29 - - i/o pmia7 - - c31 - - vref refi_1 - - j28 - - i/o pmia6 - - d31 - - i/o pmia5 - - j27 - - i/o pmia4 - - f30 - - i/o pmia3 - - h27 - - i/o pmia2 - - e31 - - i/o pmia1 - - h28 - - i/o pmia0 - - f31 - - i ext_1k - - f29 - - i/o pmid35 - - e30 - - i/o pmid34 - - f28 - - i/o pmid33 - - d30 - - i/o pmid32 - - e27 - - i/o pmid31 - - c30 - - i/o pmid30 - - f27 - - i/o pmid29 - - b31 - - i/o pmid28 - - g27 - - i/o pmid27 - - a31 - - i/o pmid26 - - e26 - - i/o pmid25 - - b30 - - i/o pmid24 - - f26 - - i/o pmid23 - - a30 - - i/o pmid22 - - g26 - - i/o pmid21 - - e29 - - i/o pmid20 - - h26 - - i/o pmid19 - - e28 - - i/o pmid18 - - e25 - - i/o pmid17 - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 217 1036-pin ftsbga devices have been discontinued. d29 - - i/o pmid16 - - c29 - - vref refi_2 - - f25 - - i/o pmik - - b29 - - i/o pmikn - - g25 - - i/o pmid15 - - a29 - - i/o pmid14 - - h25 - - i/o pmid13 - - d28 - - i/o pmid12 - - e24 - - i/o pmid11 - - c28 - - i/o pmid10 - - f24 - - i/o pmid9 - - b28 - - i/o pmid8 - - g24 - - i/o pmid7 - - a28 - - i/o pmid6 - - h24 - - i/o pmid5 - - d27 - - i/o pmid4 - - e23 - - i/o pmid3 - - c27 - - i/o pmid2 - - f23 - - i/o pmid1 - - b27 - - i/o pmid0 - - a27 - - vref refi_3 - - g23 - - i/o pmic - - d26 - - i/o pmicn - - h23 - - i/o pmiq35 - - c26 - - i/o pmiq34 - - e22 - - i/o pmiq33 - - b26 - - i/o pmiq32 - - f22 - - i/o pmiq31 - - a26 - - i/o pmiq30 - - e21 - - i/o pmiq29 - - d25 - - i/o pmiq28 - - g22 - - i/o pmiq27 - - c25 - - i/o pmiq26 - - f21 - - i/o pmiq25 - - b25 - - i/o pmiq24 - - g20 - - i/o pmiq23 - - a25 - - i/o pmiq22 - - f20 - - i/o pmiq21 - - d24 - - i/o pmiq20 - - e20 - - i/o pmiq19 - - c24 - - i/o pmiq18 - - g21 - - i/o pmiq17 - - b24 - - i/o pmiq16 - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 218 1036-pin ftsbga devices have been discontinued. h22 - - i/o mcrefclk - - a24 - - i/o spare_2 - - e19 - - i/o pmiq15 - - d23 - - vref refi_4 - - f19 - - i/o pmiq14 - - c23 - - i/o pmiq13 - - g19 - - i/o pmiq12 - - b23 - - vdda_pll vdda_pll - - h21 - - i/o pmiq11 - - a23 - - vss vss - - h20 - - i/o pmiq10 - - d22 - - i/o pmiq9 - - h19 - - i/o pmiq8 - - c22 - - i/o pmiq7 - - h18 - - i/o pmiq6 - - b22 - - i/o pmiq5 - - e18 - - i/o pmiq4 - - a22 - - i/o pmiq3 - - f18 - - i/o pmiq2 - - c21 - - i/o pmiq1 - - g18 - - i/o pmiq0 - - b21 1 (tc) 7 io pt46d - l123c a21 1 (tc) 7 io pt46c - l123t a20 1 (tc) 7 io pt45d vref_1_07 l124c a19 1 (tc) 7 io pt45c - l124t c20 1 (tc) 8 io pt44d - l125c b20 1 (tc) 8 io pt44c - l125t b19 1 (tc) 8 io pt43d - l126c a18 1 (tc) 8 io pt43c - l126t c19 1 (tc) 8 io pt42d vref_1_08 l127c d19 1 (tc) 8 io pt42c - l127t b18 1 (tc) 9 io pt41d - l128c a17 1 (tc) 9 io pt41c - l128t c18 1 (tc) 9 io pt40d - l129c d18 1 (tc) 9 io pt40c vref_1_09 l129t b17 1 (tc) 9 io pt39d - l130c c17 1 (tc) 9 io pt39c - l130t a16 1 (tc) 10 io pt38d - l131c b16 1 (tc) 10 io pt38c vref_1_10 l131t a15 1 (tc) 10 io pt37d - l132c b15 1 (tc) 10 io pt37c - l132t a14 1 (tc) 10 io pt36d - l133c b14 1 (tc) 10 io pt36c - l133t table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 219 1036-pin ftsbga devices have been discontinued. e17 1 (tc) 1 io pt35d - l134c h17 1 (tc) 1 io pt35b - l135c e16 1 (tc) 1 io pt35c - l134t g17 1 (tc) 1 io pt35a - l135t c16 1 (tc) 1 io pt34d vref_1_01 l136c g15 1 (tc) 1 io pt34b - l137c c15 1 (tc) 1 io pt34c - l136t f15 1 (tc) 1 io pt34a - l137t d17 1 (tc) 1 io pt33d - l138c f14 1 (tc) 1 io pt33b - l139c d16 1 (tc) 1 io pt33c - l138t g14 1 (tc) 1 io pt33a - l139t f17 1 (tc) 2 io pt32d - l140c h16 1 (tc) 2 io pt32b - l141c f16 1 (tc) 2 io pt32c vref_1_02 l140t g16 1 (tc) 2 io pt32a - l141t a13 1 (tc) 2 io pt31d - l142c f13 1 (tc) 2 io pt31b - l143c b13 1 (tc) 2 io pt31c - l142t f12 1 (tc) 2 io pt31a - l143t c14 1 (tc) 2 io pt30d - l144c g13 1 (tc) 2 io pt30b - l145c c13 1 (tc) 2 io pt30c - l144t h13 1 (tc) 2 io pt30a - l145t d15 1 (tc) 3 io pt29d - l146c g12 1 (tc) 3 io pt29b - l147c d14 1 (tc) 3 io pt29c vref_1_03 l146t h12 1 (tc) 3 io pt29a - l147t a12 1 (tc) 3 io pt28d - l148c h15 1 (tc) 3 io pt28b - l149c b12 1 (tc) 3 io pt28c - l148t h14 1 (tc) 3 io pt28a - l149t d13 1 (tc) 3 io pt27d - l150c d12 1 (tc) 3 io pt27c - l150t e15 1 (tc) 4 io pt26d - l151c e14 1 (tc) 4 io pt26c - l151t a11 1 (tc) 4 io pt25d - l152c j14 1 (tc) 4 io pt25b - l153c a10 1 (tc) 4 io pt25c - l152t j13 1 (tc) 4 io pt25a - l153t c12 1 (tc) 4 io pt24d - l154c c11 1 (tc) 4 io pt24c vref_1_04 l154t b11 1 (tc) 5 io pt23d ptck1c l155c table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 220 1036-pin ftsbga devices have been discontinued. b10 1 (tc) 5 io pt23c ptck1t l155t e13 1 (tc) 5 io pt22d ptck0c l156c e12 1 (tc) 5 io pt22c ptck0t l156t a9 1 (tc) 5 io pt21d vref_1_05 l157c b9 1 (tc) 5 io pt21c - l157t c10 1 (tc) 6 io pt20d - l158c c9 1 (tc) 6 io pt20c - l158t d11 1 (tc) 6 io pt19d - l159c d10 1 (tc) 6 io pt19c vref_1_06 l159t a8 0 (tl) 1 io pt18d mpi_rtry_n l160c b8 0 (tl) 1 io pt18c mpi_ack_n l160t h11 0 (tl) 1 io pt17d - l161c g11 0 (tl) 1 io pt17c vref_0_01 l161t h10 0 (tl) 1 io pt16d m0 l162c g10 0 (tl) 1 io pt16c m1 l162t a7 0 (tl) 2 io pt15d mpi_clk l163c b7 0 (tl) 2 io pt15c a21/mpi_burst_n l163t c8 0 (tl) 2 io pt14d m2 l164c c7 0 (tl) 2 io pt14c m3 l164t e11 0 (tl) 2 io pt13d vref_0_02 l165c e10 0 (tl) 2 io pt13c mpi_tea_n l165t f11 0 (tl) 3 io pt12d - l166c f10 0 (tl) 3 io pt12c - l166t d9 0 (tl) 3 io pt11d vref_0_03 l167c d8 0 (tl) 3 io pt11c - l167t h9 0 (tl) 3 io pt10d d0 l168c g9 0 (tl) 3 io pt10c tms l168t h7 0 (tl) 4 io pt9d a20/mpi_bdip_n l169c g7 0 (tl) 4 io pt9c a19/mpi_tsz1 l169t a6 0 (tl) 4 io pt8d a18/mpi_tsz0 l170c b6 0 (tl) 4 io pt8c d3 l170t e9 0 (tl) 4 io pt7d vref_0_04 l171c e8 0 (tl) 4 io pt7c - l171t f9 0 (tl) 5 io pt6d d1 l172c f8 0 (tl) 5 io pt6c d2 l172t c6 0 (tl) 5 io pt5d - l173c c5 0 (tl) 5 io pt5c vref_0_05 l173t d7 0 (tl) 5 io pt4d tdi l174c d6 0 (tl) 5 io pt4c tck l174t e7 0 (tl) 6 io pt3d - l175c g8 0 (tl) 6 io pt3b - l176c e6 0 (tl) 6 io pt3c vref_0_06 l175t h8 0 (tl) 6 io pt3a - l176t table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 221 1036-pin ftsbga devices have been discontinued. f7 0 (tl) 6 io pt2d pll_ck1c/ppll l177c f6 0 (tl) 6 io pt2c pll_ck1t/ppll l177t g5 - - o pcfg_mpi_irq cfg_irq_n/mpi_i rq_n - g6 - - io pcclk cclk - f5 - - io pdone done - aa24 - - vdd15 vdd15 - - aa8 - - vdd15 vdd15 - - aa9 - - vdd15 vdd15 - - ab8 - - vdd15 vdd15 - - ab9 - - vdd15 vdd15 - - ac13 - - vdd15 vdd15 - - ac14 - - vdd15 vdd15 - - ac15 - - vdd15 vdd15 - - ac16 - - vdd15 vdd15 - - ac17 - - vdd15 vdd15 - - ac18 - - vdd15 vdd15 - - ac19 - - vdd15 vdd15 - - ac23 - - vdd15 vdd15 - - ac8 - - vdd15 vdd15 - - ac9 - - vdd15 vdd15 - - ad10 - - vdd15 vdd15 - - ad11 - - vdd15 vdd15 - - ad12 - - vdd15 vdd15 - - ad13 - - vdd15 vdd15 - - ad14 - - vdd15 vdd15 - - ad15 - - vdd15 vdd15 - - ad16 - - vdd15 vdd15 - - ad17 - - vdd15 vdd15 - - ad18 - - vdd15 vdd15 - - ad19 - - vdd15 vdd15 - - ad20 - - vdd15 vdd15 - - ad21 - - vdd15 vdd15 - - ad22 - - vdd15 vdd15 - - ad23 - - vdd15 vdd15 - - ad8 - - vdd15 vdd15 - - ae10 - - vdd15 vdd15 - - ae11 - - vdd15 vdd15 - - ae12 - - vdd15 vdd15 - - ae13 - - vdd15 vdd15 - - ae14 - - vdd15 vdd15 - - ae15 - - vdd15 vdd15 - - ae16 - - vdd15 vdd15 - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 222 1036-pin ftsbga devices have been discontinued. ae17 - - vdd15 vdd15 - - ae18 - - vdd15 vdd15 - - ae19 - - vdd15 vdd15 - - ae20 - - vdd15 vdd15 - - ae21 - - vdd15 vdd15 - - ae22 - - vdd15 vdd15 - - ae23 - - vdd15 vdd15 - - ae9 - - vdd15 vdd15 - - k10 - - vdd15 vdd15 - - k11 - - vdd15 vdd15 - - k12 - - vdd15 vdd15 - - k9 - - vdd15 vdd15 - - l10 - - vdd15 vdd15 - - l11 - - vdd15 vdd15 - - l12 - - vdd15 vdd15 - - l13 - - vdd15 vdd15 - - l14 - - vdd15 vdd15 - - l15 - - vdd15 vdd15 - - l16 - - vdd15 vdd15 - - l8 - - vdd15 vdd15 - - m13 - - vdd15 vdd15 - - m14 - - vdd15 vdd15 - - m8 - - vdd15 vdd15 - - m9 - - vdd15 vdd15 - - n8 - - vdd15 vdd15 - - n9 - - vdd15 vdd15 - - p8 - - vdd15 vdd15 - - p9 - - vdd15 vdd15 - - r8 - - vdd15 vdd15 - - r9 - - vdd15 vdd15 - - t8 - - vdd15 vdd15 - - t9 - - vdd15 vdd15 - - u8 - - vdd15 vdd15 - - u9 - - vdd15 vdd15 - - v24 - - vdd15 vdd15 - - v8 - - vdd15 vdd15 - - v9 - - vdd15 vdd15 - - w24 - - vdd15 vdd15 - - w8 - - vdd15 vdd15 - - w9 - - vdd15 vdd15 - - y24 - - vdd15 vdd15 - - y8 - - vdd15 vdd15 - - y9 - - vdd15 vdd15 - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 223 1036-pin ftsbga devices have been discontinued. aa25 - - vdd33 vdd33 - - ab24 - - vdd33 vdd33 - - ab25 - - vdd33 vdd33 - - ac24 - - vdd33 vdd33 - - ac25 - - vdd33 vdd33 - - ad24 - - vdd33 vdd33 - - ad25 - - vdd33 vdd33 - - ae24 - - vdd33 vdd33 - - ae25 - - vdd33 vdd33 - - af22 - - vdd33 vdd33 - - af23 - - vdd33 vdd33 - - af24 - - vdd33 vdd33 - - af25 - - vdd33 vdd33 - - ag23 - - vdd33 vdd33 - - ag24 - - vdd33 vdd33 - - ag25 - - vdd33 vdd33 - - ah22 - - vdd33 vdd33 - - n24 - - vdd33 vdd33 - - n25 - - vdd33 vdd33 - - p24 - - vdd33 vdd33 - - p25 - - vdd33 vdd33 - - r24 - - vdd33 vdd33 - - r25 - - vdd33 vdd33 - - t24 - - vdd33 vdd33 - - t25 - - vdd33 vdd33 - - u24 - - vdd33 vdd33 - - u25 - - vdd33 vdd33 - - v25 - - vdd33 vdd33 - - w25 - - vdd33 vdd33 - - y25 - - vdd33 vdd33 - - j7 - - vdd33 vdd33_fpgapll - - k8 - - vdd33 vdd33_fpgapll - - ae8 - - vdd33 vdd33_fpgapll - - af7 - - vdd33 vdd33_fpgapll - - ah20 - - vdd33 vdd33_fpgapll - - ah21 - - vdd33 vdd33_fpgapll - - d20 - - vdd33 vdd33_fpgapll - - d21 - - vdd33 vdd33_fpgapll - - j19 - - vddh vddh - - j20 - - vddh vddh - - j21 - - vddh vddh - - j23 - - vddh vddh - - j25 - - vddh vddh - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 224 1036-pin ftsbga devices have been discontinued. k19 - - vddh vddh - - k20 - - vddh vddh - - k21 - - vddh vddh - - k23 - - vddh vddh - - k25 - - vddh vddh - - l18 - - vddh vddh - - l19 - - vddh vddh - - l20 - - vddh vddh - - l21 - - vddh vddh - - l23 - - vddh vddh - - m18 - - vddh vddh - - m19 - - vddh vddh - - m20 - - vddh vddh - - m21 - - vddh vddh - - m23 - - vddh vddh - - m25 - - vddh vddh - - n18 - - vddh vddh - - n19 - - vddh vddh - - n20 - - vddh vddh - - n21 - - vddh vddh - - n23 - - vddh vddh - - p18 - - vddh vddh - - p19 - - vddh vddh - - p20 - - vddh vddh - - p21 - - vddh vddh - - j10 0 (tl) - vddio0 vddio0 - - j11 0 (tl) - vddio0 vddio0 - - j12 0 (tl) - vddio0 vddio0 - - j8 0 (tl) - vddio0 vddio0 - - j9 0 (tl) - vddio0 vddio0 - - k7 0 (tl) - vddio0 vddio0 - - l7 0 (tl) - vddio0 vddio0 - - m7 0 (tl) - vddio0 vddio0 - - n7 0 (tl) - vddio0 vddio0 - - p7 0 (tl) - vddio0 vddio0 - - j15 0 (tl) - vddio1 vddio1 - - j16 0 (tl) - vddio1 vddio1 - - j17 0 (tl) - vddio1 vddio1 - - j18 0 (tl) - vddio1 vddio1 - - k13 0 (tl) - vddio1 vddio1 - - k14 0 (tl) - vddio1 vddio1 - - k15 0 (tl) - vddio1 vddio1 - - k16 0 (tl) - vddio1 vddio1 - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 225 1036-pin ftsbga devices have been discontinued. k17 0 (tl) - vddio1 vddio1 - - k18 0 (tl) - vddio1 vddio1 - - af15 0 (tl) - vddio5 vddio5 - - af16 0 (tl) - vddio5 vddio5 - - af17 0 (tl) - vddio5 vddio5 - - af18 0 (tl) - vddio5 vddio5 - - af19 0 (tl) - vddio5 vddio5 - - af20 0 (tl) - vddio5 vddio5 - - af21 0 (tl) - vddio5 vddio5 - - ag19 0 (tl) - vddio5 vddio5 - - ag20 0 (tl) - vddio5 vddio5 - - ag21 0 (tl) - vddio5 vddio5 - - ac7 0 (tl) - vddio6 vddio6 - - ad7 0 (tl) - vddio6 vddio6 - - ae7 0 (tl) - vddio6 vddio6 - - af10 0 (tl) - vddio6 vddio6 - - af11 0 (tl) - vddio6 vddio6 - - af12 0 (tl) - vddio6 vddio6 - - af13 0 (tl) - vddio6 vddio6 - - af14 0 (tl) - vddio6 vddio6 - - af8 0 (tl) - vddio6 vddio6 - - af9 0 (tl) - vddio6 vddio6 - - aa7 0 (tl) - vddio7 vddio7 - - ab7 0 (tl) - vddio7 vddio7 - - r7 0 (tl) - vddio7 vddio7 - - t7 0 (tl) - vddio7 vddio7 - - u6 0 (tl) - vddio7 vddio7 - - u7 0 (tl) - vddio7 vddio7 - - v6 0 (tl) - vddio7 vddio7 - - v7 0 (tl) - vddio7 vddio7 - - w7 0 (tl) - vddio7 vddio7 - - y7 0 (tl) - vddio7 vddio7 - - b5 - - nc - - d5 - - nc - - c34 - - nc - - d4 - - nc - - d3 - - nc - - d2 - - nc - - e5 - - nc - - e4 - - nc - - e3 - - nc - - e2 - - nc - - e1 - - nc - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 226 1036-pin ftsbga devices have been discontinued. f3 - - nc - - b4 - - nc - - f2 - - nc - - f1 - - nc - - g3 - - nc - - p6 - - nc - - n6 - - nc - - m6 - - nc - - a5 - - nc - - l6 - - nc - - k6 - - nc - - al5 - - nc - - al4 - - nc - - al3 - - nc - - al2 - - nc - - al1 - - nc - - ak5 - - nc - - ak4 - - nc - - ak3 - - nc - - a4 - - nc - - ak2 - - nc - - ak1 - - nc - - am5 - - nc - - am4 - - nc - - am3 - - nc - - am2 - - nc - - an4 - - nc - - an3 - - nc - - ap4 - - nc - - aj5 - - nc - - b3 - - nc - - aj4 - - nc - - ah5 - - nc - - ag5 - - nc - - ag6 - - nc - - aj20 - - nc - - aj25 - - nc - - aj24 - - nc - - aj23 - - nc - - aj22 - - nc - - aj21 - - nc - - c4 - - nc - - aj29 - - nc - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 227 1036-pin ftsbga devices have been discontinued. aj28 - - nc - - aj27 - - nc - - aj26 - - nc - - ah27 - - nc - - ah26 - - nc - - ag27 - - nc - - ag26 - - nc - - af27 - - nc - - af26 - - nc - - c3 - - nc - - ah25 - - nc - - ah29 - - nc - - ah28 - - nc - - ak29 - - nc - - ak28 - - nc - - ak27 - - nc - - ak26 - - nc - - ak25 - - nc - - ap29 - - nc - - ap28 - - nc - - c2 - - nc - - ap27 - - nc - - ap26 - - nc - - an29 - - nc - - an28 - - nc - - an27 - - nc - - an26 - - nc - - am29 - - nc - - am28 - - nc - - am27 - - nc - - am26 - - nc - - d1 - - nc - - al29 - - nc - - al28 - - nc - - al27 - - nc - - al26 - - nc - - a32 - - nc - - a33 - - nc - - a34 - - nc - - al30 - - nc - - b34 - - nc - - b33 - - nc - - a1 - - vss vss - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 228 1036-pin ftsbga devices have been discontinued. a2 - - vss vss - - a3 - - vss vss - - aa10 - - vss vss - - aa11 - - vss vss - - aa12 - - vss vss - - aa13 - - vss vss - - aa14 - - vss vss - - aa15 - - vss vss - - aa16 - - vss vss - - aa17 - - vss vss - - aa18 - - vss vss - - aa19 - - vss vss - - aa20 - - vss vss - - aa21 - - vss vss - - aa22 - - vss vss - - aa23 - - vss vss - - ab10 - - vss vss - - ab11 - - vss vss - - ab12 - - vss vss - - ab13 - - vss vss - - ab14 - - vss vss - - ab15 - - vss vss - - ab16 - - vss vss - - ab17 - - vss vss - - ab18 - - vss vss - - ab19 - - vss vss - - ab20 - - vss vss - - ab21 - - vss vss - - ab22 - - vss vss - - ab23 - - vss vss - - ac10 - - vss vss - - ac11 - - vss vss - - ac12 - - vss vss - - ac20 - - vss vss - - ac21 - - vss vss - - ac22 - - vss vss - - ad9 - - vss vss - - am1 - - vss vss - - am30 - - vss vss - - am34 - - vss vss - - an1 - - vss vss - - an2 - - vss vss - - an30 - - vss vss - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 229 1036-pin ftsbga devices have been discontinued. an31 - - vss vss - - an32 - - vss vss - - an33 - - vss vss - - an34 - - vss vss - - ap1 - - vss vss - - ap2 - - vss vss - - ap3 - - vss vss - - ap30 - - vss vss - - ap31 - - vss vss - - ap32 - - vss vss - - ap33 - - vss vss - - ap34 - - vss vss - - b1 - - vss vss - - b2 - - vss vss - - c1 - - vss vss - - l17 - - vss vss - - l9 - - vss vss - - m10 - - vss vss - - m11 - - vss vss - - m12 - - vss vss - - m15 - - vss vss - - m16 - - vss vss - - m17 - - vss vss - - n10 - - vss vss - - n11 - - vss vss - - n12 - - vss vss - - n13 - - vss vss - - n14 - - vss vss - - n15 - - vss vss - - n16 - - vss vss - - n17 - - vss vss - - p10 - - vss vss - - p11 - - vss vss - - p12 - - vss vss - - p13 - - vss vss - - p14 - - vss vss - - p15 - - vss vss - - p16 - - vss vss - - p17 - - vss vss - - r10 - - vss vss - - r11 - - vss vss - - r12 - - vss vss - - r13 - - vss vss - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 230 1036-pin ftsbga devices have been discontinued. r14 - - vss vss - - r15 - - vss vss - - r16 - - vss vss - - r17 - - vss vss - - t10 - - vss vss - - t11 - - vss vss - - t12 - - vss vss - - t13 - - vss vss - - t14 - - vss vss - - t15 - - vss vss - - t16 - - vss vss - - t17 - - vss vss - - u10 - - vss vss - - u11 - - vss vss - - u12 - - vss vss - - u13 - - vss vss - - u14 - - vss vss - - u15 - - vss vss - - u16 - - vss vss - - u17 - - vss vss - - u18 - - vss vss - - v10 - - vss vss - - v11 - - vss vss - - v12 - - vss vss - - v13 - - vss vss - - v14 - - vss vss - - v15 - - vss vss - - v16 - - vss vss - - v17 - - vss vss - - v18 - - vss vss - - v19 - - vss vss - - v20 - - vss vss - - v21 - - vss vss - - v22 - - vss vss - - v23 - - vss vss - - w10 - - vss vss - - w11 - - vss vss - - w12 - - vss vss - - w13 - - vss vss - - w14 - - vss vss - - w15 - - vss vss - - w16 - - vss vss - - w17 - - vss vss - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 231 1036-pin ftsbga devices have been discontinued. w18 - - vss vss - - w19 - - vss vss - - w20 - - vss vss - - w21 - - vss vss - - w22 - - vss vss - - w23 - - vss vss - - y10 - - vss vss - - y11 - - vss vss - - y12 - - vss vss - - y13 - - vss vss - - y14 - - vss vss - - y15 - - vss vss - - y16 - - vss vss - - y17 - - vss vss - - y18 - - vss vss - - y19 - - vss vss - - y20 - - vss vss - - y21 - - vss vss - - y22 - - vss vss - - y23 - - vss vss - - j22 - - vss vss - - j24 - - vss vss - - j26 - - vss vss - - k22 - - vss vss - - k24 - - vss vss - - l22 - - vss vss - - l24 - - vss vss - - l25 - - vss vss - - m22 - - vss vss - - m24 - - vss vss - - n22 - - vss vss - - p22 - - vss vss - - p23 - - vss vss - - r18 - - vss vss - - r19 - - vss vss - - r20 - - vss vss - - r21 - - vss vss - - r22 - - vss vss - - r23 - - vss vss - - t18 - - vss vss - - t19 - - vss vss - - t20 - - vss vss - - t21 - - vss vss - - table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 232 1036-pin ftsbga devices have been discontinued. t22 - - vss vss - - t23 - - vss vss - - u19 - - vss vss - - u20 - - vss vss - - u21 - - vss vss - - u22 - - vss vss - - u23 - - vss vss - - note: all differential pairs use adjacent balls. table 86. 1156 fpbga pin table (continued) f1156 ball vddio bank vref group i/o pin description additional function f1156 pair lattice semiconductor orca orspi4 data sheet 233 1036-pin ftsbga devices have been discontinued. table 87. 1036 ftsbga pin table fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair j44 - - vdd33 vdd33_fpgapll - - k42 - - o prd_data rd_data/tdo - j43 - - i preset_n reset_n - k43 - - i prd_cfg_n rd_cfg_n - k44 - - i pprgrm_n prgrm_n - m42 0 (tl) 7 io pl2d pll_ck0c/hppll l1c m41 0 (tl) 7 io pl2c pll_ck0t/hppll l1t m40 0 (tl) 7 io pl3d - l3c l38 0 (tl) 7 io pl3b - l4c a1 - - vss vss - - m39 0 (tl) 7 io pl3c vref_0_07 l3t l39 0 (tl) 7 io pl3a - l4t n42 0 (tl) 7 io pl4d d5 l5c g30 0 (tl) - vddio0 vddio0 - - n41 0 (tl) 7 io pl4c d6 l5t n40 0 (tl) 8 io pl5d - l7c l40 0 (tl) 8 io pl5b - l8c a2 - - vss vss - - n39 0 (tl) 8 io pl5c vref_0_08 l7t l41 0 (tl) 8 io pl5a - l8t p44 0 (tl) 8 io pl6d hdc l9c c42 - - vdd15 vdd15 - - p43 0 (tl) 8 io pl6c ldc_n l9t p42 0 (tl) 8 io pl7d - l11c l42 0 (tl) 8 io pl7b - l12c g31 0 (tl) - vddio0 vddio0 - - p41 0 (tl) 8 io pl7c - l11t l43 0 (tl) 8 io pl7a - l12t r44 0 (tl) 9 io pl8d testcfg l13c a11 - - vss vss - - r43 0 (tl) 9 io pl8c d7 l13t r42 0 (tl) 9 io pl9d vref_0_09 l15c m43 0 (tl) 9 io pl9b - l16c d42 - - vdd15 vdd15 - - r41 0 (tl) 9 io pl9c a17/ppc_a31 l15t m44 0 (tl) 9 io pl9a - l16t t44 0 (tl) 9 io pl10d cs0_n l17c g36 0 (tl) - vddio0 vddio0 - - t43 0 (tl) 9 io pl10c cs1 l17t t42 0 (tl) 10 io pl11d - l19c n44 0 (tl) 10 io pl11b - l20c a22 - - vss vss - - lattice semiconductor orca orspi4 data sheet 234 1036-pin ftsbga devices have been discontinued. t41 0 (tl) 10 io pl11c - l19t n43 0 (tl) 10 io pl11a - l20t u44 0 (tl) 10 io pl12d init_n l21c e40 - - vdd15 vdd15 - - u43 0 (tl) 10 io pl12c dout l21t u42 0 (tl) 10 io pl13d vref_0_10 l23c p40 0 (tl) 10 io pl13b - l24c u41 0 (tl) 10 io pl13c a16/ppc_a30 l23t p39 0 (tl) 10 io pl13a - l24t v44 7 (cl) 1 io pl14d a15/ppc_a29 l25c b2 - - vss vss - - v43 7 (cl) 1 io pl14c a14/ppc_a28 l25t g34 - - vss vss - - v42 7 (cl) 1 io pl15d - l27c r40 7 (cl) 1 io pl15b - l28c g35 - - vdd15 vdd15 - - v41 7 (cl) 1 io pl15c - l27t r39 7 (cl) 1 io pl15a - l28t w44 7 (cl) 1 io pl16d vref_7_01 l29c t40 7 (cl) 1 io pl16b - l30c w38 7 (cl) - vddio7 vddio7 - - w43 7 (cl) 1 io pl16c d4 l29t t39 7 (cl) 1 io pl16a - l30t w42 7 (cl) 2 io pl17d - l31c u40 7 (cl) 2 io pl17b - l32c b43 - - vss vss - - w41 7 (cl) 2 io pl17c - l31t u39 7 (cl) 2 io pl17a - l32t y44 7 (cl) 2 io pl18d rdy/busy_n/rclk l33c v40 7 (cl) 2 io pl18b - l34c g37 - - vdd15 vdd15 - - y43 7 (cl) 2 io pl18c vref_7_02 l33t v39 7 (cl) 2 io pl18a - l34t y42 7 (cl) 2 io pl19d a13/ppc_a27 l35c w40 7 (cl) 2 io pl19b - l36c y38 7 (cl) - vddio7 vddio7 - - y41 7 (cl) 2 io pl19c a12/ppc_a26 l35t w39 7 (cl) 2 io pl19a - l36t aa44 7 (cl) 3 io pl20d - l37c y40 7 (cl) 3 io pl20b - l38c b44 - - vss vss - - aa43 7 (cl) 3 io pl20c - l37t y39 7 (cl) 3 io pl20a - l38t table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 235 1036-pin ftsbga devices have been discontinued. aa42 7 (cl) 3 io pl21d a11/ppc_a25 l39c aa40 7 (cl) 3 io pl21b - l40c h38 - - vdd15 vdd15 - - aa41 7 (cl) 3 io pl21c vref_7_03 l39t aa39 7 (cl) 3 io pl21a - l40t ab44 7 (cl) 3 io pl22d - l41c ab40 7 (cl) 3 io pl22b - l42c ab38 7 (cl) - vddio7 vddio7 - - ab43 7 (cl) 3 io pl22c - l41t ab39 7 (cl) 3 io pl22a - l42t ab42 7 (cl) 4 io pl23d rd_n/mpi_strb_ n l43c ac40 7 (cl) 4 io pl23b - l44c g20 - - vss vss - - ab41 7 (cl) 4 io pl23c vref_7_04 l43t ac39 7 (cl) 4 io pl23a - l44t ac44 7 (cl) 4 io pl24d plck0c l45c ad40 7 (cl) 4 io pl24b - l46c ac43 7 (cl) 4 io pl24c plck0t l45t ad39 7 (cl) 4 io pl24a - l46t ac42 7 (cl) 5 io pl25d a10/ppc_a24 l47c ae40 7 (cl) 5 io pl25b - l48c ac38 7 (cl) - vddio7 vddio7 - - ac41 7 (cl) 5 io pl25c a9/ppc_a23 l47t ae39 7 (cl) 5 io pl25a - l48t ad44 7 (cl) 5 io pl26d a8/ppc_a22 l49c af40 7 (cl) 5 io pl26b - l50c g23 - - vss vss - - ad43 7 (cl) 5 io pl26c vref_7_05 l49t af39 7 (cl) 5 io pl26a - l50t ad42 7 (cl) 5 io pl27d - l51c ag44 7 (cl) 5 io pl27b - l52c j38 - - vdd15 vdd15 - - ad41 7 (cl) 5 io pl27c - l51t ag43 7 (cl) 5 io pl27a - l52t ae44 7 (cl) 6 io pl28d plck1c l53c ag42 7 (cl) 6 io pl28b - l54c ae38 7 (cl) - vddio7 vddio7 - - ae43 7 (cl) 6 io pl28c plck1t l53t ag41 7 (cl) 6 io pl28a - l54t ae42 7 (cl) 6 io pl29d vref_7_06 l55c ag40 7 (cl) 6 io pl29b - l56c g26 - - vss vss - - table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 236 1036-pin ftsbga devices have been discontinued. ae41 7 (cl) 6 io pl29c a7/ppc_a21 l55t ag39 7 (cl) 6 io pl29a - l56t af44 7 (cl) 6 io pl30d a6/ppc_a20 l57c ah40 7 (cl) 6 io pl30b - l58c n38 - - vdd15 vdd15 - - af43 7 (cl) 6 io pl30c a5/ppc_a19 l57t ah39 7 (cl) 6 io pl30a - l58t af42 7 (cl) 7 io pl31d - l59c aj40 7 (cl) 7 io pl31b - l60c af38 7 (cl) - vddio7 vddio7 - - af41 7 (cl) 7 io pl31c - l59t aj39 7 (cl) 7 io pl31a - l60t ah44 7 (cl) 7 io pl32d wr_n/mpi_rw l61c ak42 7 (cl) 7 io pl32b - l62c g29 - - vss vss - - ah43 7 (cl) 7 io pl32c vref_7_07 l61t ak41 7 (cl) 7 io pl32a - l62t ah42 7 (cl) 7 io pl33d - l63c ak40 7 (cl) 7 io pl33b - l64c r7 - - vdd15 vdd15 - - ah41 7 (cl) 7 io pl33c - l63t ak39 7 (cl) 7 io pl33a - l64t aj44 7 (cl) 8 io pl34d a4/ppc_a18 l65c aj43 7 (cl) 8 io pl34c vref_7_08 l65t aj42 7 (cl) 8 io pl35d a3/ppc_a17 l67c am44 7 (cl) 8 io pl35b - l68c g32 - - vss vss - - aj41 7 (cl) 8 io pl35c a2/ppc_a16 l67t am43 7 (cl) 8 io pl35a - l68t ak44 7 (cl) 8 io pl36d a1/ppc_a15 l69c al40 7 (cl) 8 io pl36b - l70c t38 - - vdd15 vdd15 - - ak43 7 (cl) 8 io pl36c a0/ppc_a14 l69t al39 7 (cl) 8 io pl36a - l70t al44 7 (cl) 8 io pl37d dp0 l71c an43 7 (cl) 8 io pl37b - l72c al43 7 (cl) 8 io pl37c dp1 l71t ap43 7 (cl) 8 io pl37a - l72t al42 6 (bl) 1 io pl38d d8 l73c ar43 6 (bl) 1 io pl38b - l74c ab1 - - vss vss - - al41 6 (bl) 1 io pl38c vref_6_01 l73t ar42 6 (bl) 1 io pl38a - l74t table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 237 1036-pin ftsbga devices have been discontinued. am42 6 (bl) 1 io pl39d d9 l75c an40 6 (bl) 1 io pl39b - l76c u7 - - vdd15 vdd15 - - am41 6 (bl) 1 io pl39c d10 l75t an39 6 (bl) 1 io pl39a - l76t am40 6 (bl) 2 io pl40d - l77c ap40 6 (bl) 2 io pl40b - l78c aj38 6 (bl) - vddio6 vddio6 - - am39 6 (bl) 2 io pl40c vref_6_02 l77t ap39 6 (bl) 2 io pl40a - l78t ap44 6 (bl) 2 io pl41d - l79c an42 6 (bl) 2 io pl41b - l80c ad7 - - vss vss - - ar44 6 (bl) 2 io pl41c - l79t an41 6 (bl) 2 io pl41a - l80t ap42 6 (bl) 3 io pl42d d11 l81c at44 6 (bl) 3 io pl42b - l82c y7 - - vdd15 vdd15 - - ap41 6 (bl) 3 io pl42c d12 l81t at43 6 (bl) 3 io pl42a - l82t au44 6 (bl) 3 io pl43d - l83c av44 6 (bl) 3 io pl43b - l84c am38 6 (bl) - vddio6 vddio6 - - au43 6 (bl) 3 io pl43c - l83t av43 6 (bl) 3 io pl43a - l84t au42 6 (bl) 3 io pl44d vref_6_03 l85c aw44 6 (bl) 4 io pl44b - l86c ad38 - - vss vss - - at42 6 (bl) 3 io pl44c d13 l85t ay44 6 (bl) 4 io pl44a - l86t ar41 6 (bl) 4 io pl45d - l87c bb44 6 (bl) 4 io pl45b - l88c ac7 - - vdd15 vdd15 - - ar40 6 (bl) 4 io pl45c vref_6_04 l87t ba44 6 (bl) 4 io pl45a - l88t au41 6 (bl) 4 io pl46d - l89c ar38 6 (bl) - vddio6 vddio6 - - at41 6 (bl) 4 io pl46c - l89t at40 6 (bl) 4 io pl47d pll_ck7c/hppll l91c ag7 - - vss vss - - at39 6 (bl) 4 io pl47c pll_ck7t/hppll l91t ag38 - - vss vss - - ar39 - - i ptemp ptemp - table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 238 1036-pin ftsbga devices have been discontinued. av29 6 (bl) - vddio6 vddio6 - - ae7 - - vdd15 vdd15 - - bc33 - - io lvds_r lvds_r - ba42 - - vdd33 vdd33_fpgapll - - ak7 - - vss vss - - av42 - - vdd33 vdd33_fpgapll - - ah38 - - vdd15 vdd15 - - bb43 6 (bl) 5 io pb2a dp2 l93t bc42 6 (bl) 5 io pb2c pll_ck6t/ppll l94t av32 6 (bl) - vddio6 vddio6 - - ba43 6 (bl) 5 io pb2b - l93c bd42 6 (bl) 5 io pb2d pll_ck6c/ppll l94c bc41 6 (bl) 5 io pb3c - l96t ak38 - - vss vss - - bd41 6 (bl) 5 io pb3d - l96c bc40 6 (bl) 5 io pb4c vref_6_05 l98t aj7 - - vdd15 vdd15 - - bd40 6 (bl) 5 io pb4d dp3 l98c aw43 6 (bl) 6 io pb5a - l99t ba37 6 (bl) 6 io pb5c - l100t av35 6 (bl) - vddio6 vddio6 - - ay43 6 (bl) 6 io pb5b - l99c bb37 6 (bl) 6 io pb5d - l100c aw42 6 (bl) 6 io pb6a - l101t bc37 6 (bl) 6 io pb6c vref_6_06 l102t an1 - - vss vss - - ay42 6 (bl) 6 io pb6b - l101c bd37 6 (bl) 6 io pb6d d14 l102c aw41 6 (bl) 6 io pb7a - l103t ba36 6 (bl) 6 io pb7c - l104t al38 - - vdd15 vdd15 - - av41 6 (bl) 6 io pb7b - l103c bb36 6 (bl) 6 io pb7d - l104c ay41 6 (bl) 7 io pb8a - l105t bc36 6 (bl) 7 io pb8c d15 l106t ba41 6 (bl) 7 io pb8b - l105c bd36 6 (bl) 7 io pb8d d16 l106c au40 6 (bl) 7 io pb9a - l107t ba35 6 (bl) 7 io pb9c d17 l108t an7 - - vss vss - - au39 6 (bl) 7 io pb9b - l107c bb35 6 (bl) 7 io pb9d d18 l108c aw40 6 (bl) 7 io pb10a - l109t table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 239 1036-pin ftsbga devices have been discontinued. bc35 6 (bl) 7 io pb10c vref_6_07 l110t av40 6 (bl) 7 io pb10b - l109c bd35 6 (bl) 7 io pb10d d19 l110c ba34 6 (bl) 8 io pb11c d20 l112t bb34 6 (bl) 8 io pb11d d21 l112c ba40 6 (bl) 8 io pb12a - l113t bc34 6 (bl) 8 io pb12c vref_6_08 l114t bb40 6 (bl) 8 io pb12b - l113c bd34 6 (bl) 8 io pb12d d22 l114c av39 6 (bl) 9 io pb13a - l115t ba33 6 (bl) 9 io pb13c d23 l116t aw39 6 (bl) 9 io pb13b - l115c bb33 6 (bl) 9 io pb13d d24 l116c bb39 6 (bl) 9 io pb14a - l117t ba32 6 (bl) 9 io pb14c vref_6_09 l118t ba39 6 (bl) 9 io pb14b - l117c bb32 6 (bl) 9 io pb14d d25 l118c bc39 6 (bl) 9 io pb15a - l119t bc32 6 (bl) 9 io pb15c - l120t bd39 6 (bl) 9 io pb15b - l119c bd32 6 (bl) 9 io pb15d - l120c bb38 6 (bl) 10 io pb16a - l121t ba31 6 (bl) 10 io pb16c d26 l122t ba38 6 (bl) 10 io pb16b - l121c bb31 6 (bl) 10 io pb16d d27 l122c aw38 6 (bl) 10 io pb17a - l123t bc31 6 (bl) 10 io pb17c - l124t ay38 6 (bl) 10 io pb17b - l123c bd31 6 (bl) 10 io pb17d - l124c bc38 6 (bl) 10 io pb18a - l125t ba30 6 (bl) 10 io pb18c vref_6_10 l126t bd38 6 (bl) 10 io pb18b - l125c bb30 6 (bl) 10 io pb18d d28 l126c aw37 6 (bl) 11 io pb19a - l127t bc30 6 (bl) 11 io pb19c d29 l128t ay37 6 (bl) 11 io pb19b - l127c bd30 6 (bl) 11 io pb19d d30 l128c aw36 6 (bl) 11 io pb20a - l129t ba29 6 (bl) 11 io pb20c vref_6_11 l130t ay36 6 (bl) 11 io pb20b - l129c bb29 6 (bl) 11 io pb20d d31 l130c aw35 5 (bc) 1 io pb21a - l131t bc29 5 (bc) 1 io pb21c - l132t table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 240 1036-pin ftsbga devices have been discontinued. an38 - - vss vss - - ay35 5 (bc) 1 io pb21b - l131c bd29 5 (bc) 1 io pb21d - l132c aw34 5 (bc) 1 io pb22a - l133t ba28 5 (bc) 1 io pb22c vref_5_01 l134t am7 - - vdd15 vdd15 - - ay34 5 (bc) 1 io pb22b - l133c bb28 5 (bc) 1 io pb22d - l134c aw33 5 (bc) 2 io pb23a - l135t bc28 5 (bc) 2 io pb23c pbck0t l136t av17 5 (bc) - vddio5 vddio5 - - bd28 5 (bc) 2 io pb23d pbck0c l136c ba27 5 (bc) 2 io pb24c vref_5_02 l138t ay33 5 (bc) 2 io pb24b - l137c bb27 5 (bc) 2 io pb24d - l138c aw32 5 (bc) 2 io pb25a - l139t bc27 5 (bc) 2 io pb25c - l140t ap38 - - vdd15 vdd15 - - ay32 5 (bc) 2 io pb25b - l139c bd27 5 (bc) 2 io pb25d - l140c aw31 5 (bc) 3 io pb26a - l141t ba26 5 (bc) 3 io pb26c - l142t av20 5 (bc) - vddio5 vddio5 - - ay31 5 (bc) 3 io pb26b - l141c bb26 5 (bc) 3 io pb26d vref_5_03 l142c aw30 5 (bc) 3 io pb27a - l143t bc26 5 (bc) 3 io pb27c - l144t an44 - - vss vss - - ay30 5 (bc) 3 io pb27b - l143c bd26 5 (bc) 3 io pb27d - l144c aw29 5 (bc) 3 io pb28a - l145t ba25 5 (bc) 3 io pb28c pbck1t l146t ar7 - - vdd15 vdd15 - - ay29 5 (bc) 3 io pb28b - l145c bb25 5 (bc) 3 io pb28d pbck1c l146c aw28 5 (bc) 3 io pb29a - l147t bc25 5 (bc) 4 io pb29c - l148t av21 5 (bc) - vddio5 vddio5 - - ay28 5 (bc) 3 io pb29b - l147c bd25 5 (bc) 4 io pb29d - l148c aw27 5 (bc) 4 io pb30a - l149t ba24 5 (bc) 4 io pb30c - l150t av7 - - vss vss - - table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 241 1036-pin ftsbga devices have been discontinued. ay27 5 (bc) 4 io pb30b - l149c bb24 5 (bc) 4 io pb30d vref_5_04 l150c aw26 5 (bc) 4 io pb31a - l151t bc24 5 (bc) 4 io pb31c - l152t at7 - - vdd15 vdd15 - - ay26 5 (bc) 4 io pb31b - l151c bd24 5 (bc) 4 io pb31d - l152c aw25 5 (bc) 5 io pb32a - l153t ba23 5 (bc) 5 io pb32c - l154t av23 5 (bc) - vddio5 vddio5 - - ay25 5 (bc) 5 io pb32b - l153c bb23 5 (bc) 5 io pb32d vref_5_05 l154c aw23 5 (bc) 5 io pb33a - l155t bc23 5 (bc) 5 io pb33c - l156t av18 - - vss vss - - ay23 5 (bc) 5 io pb33b - l155c bd23 5 (bc) 5 io pb33d - l156c aw24 5 (bc) 5 io pb34a - l157t ba22 5 (bc) 5 io pb34c - l158t at38 - - vdd15 vdd15 - - ay24 5 (bc) 5 io pb34b - l157c bb22 5 (bc) 5 io pb34d - l158c aw22 5 (bc) 6 io pb35a - l159t bd21 5 (bc) 6 io pb35c - l160t av25 5 (bc) - vddio5 vddio5 - - ay22 5 (bc) 6 io pb35b - l159c bc21 5 (bc) 6 io pb35d vref_5_06 l160c bd20 5 (bc) 6 io pb36c - l162t av22 - - vss vss - - bc20 5 (bc) 6 io pb36d - l162c ay21 5 (bc) 7 io pb37a - l163t bb20 5 (bc) 7 io pb37c - l164t au7 - - vdd15 vdd15 - - aw21 5 (bc) 7 io pb37b - l163c ba20 5 (bc) 7 io pb37d - l164c ba21 5 (bc) 7 io pb38a - l165t bd19 5 (bc) 7 io pb38c vref_5_07 l166t av26 5 (bc) - vddio5 vddio5 - - bb21 5 (bc) 7 io pb38b - l165c bc19 5 (bc) 7 io pb38d - l166c ay20 5 (bc) 7 io pb39a - l167t bb19 5 (bc) 7 io pb39c - l168t av24 - - vss vss - - table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 242 1036-pin ftsbga devices have been discontinued. aw20 5 (bc) 7 io pb39b - l167c ba19 5 (bc) 7 io pb39d - l168c ay19 5 (bc) 8 io pb40a - l169t bd18 5 (bc) 8 io pb40c - l170t aw19 5 (bc) 8 io pb40b - l169c bc18 5 (bc) 8 io pb40d vref_5_08 l170c ay18 5 (bc) 8 io pb41a - l171t bb18 5 (bc) 8 io pb41c - l172t aw18 5 (bc) 8 io pb41b - l171c ba18 5 (bc) 8 io pb41d - l172c ay17 5 (bc) 8 io pb42a - l173t bd17 5 (bc) 8 io pb42c - l174t av27 - - vss vss - - aw17 5 (bc) 8 io pb42b - l173c bc17 5 (bc) 8 io pb42d - l174c ay16 5 (bc) 9 io pb43a - l175t bb17 5 (bc) 9 io pb43c - l176t aw16 5 (bc) 9 io pb43b - l175c ba17 5 (bc) 9 io pb43d - l176c bd13 5 (bc) 9 io pb44a - l177t bd16 5 (bc) 9 io pb44c - l178t bc13 5 (bc) 9 io pb44b - l177c bc16 5 (bc) 9 io pb44d vref_5_09 l178c bb16 5 (bc) 9 io pb45c - l180t av30 - - vss vss - - ba16 5 (bc) 9 io pb45d - l180c bd12 5 (bc) 10 io pb46a - l181t bd14 5 (bc) 10 io pb46c - l182t bc12 5 (bc) 10 io pb46b - l181c bd15 5 (bc) 10 io pb46d vref_5_10 l182c bc15 5 (bc) 10 io pb47c pll_ck5t/ppll l184t bc14 5 (bc) 10 io pb47d pll_ck5c/ppll l184c bc11 - - vdd33 vdd33_fpgapll - - av33 - - vss vss - - bd7 - - vdd33 vdd33_fpgapll - - bd8 - - i spare_1 - - bb1 - - i resetn - - bb2 - - i tristn - - av15 - - i testmd1n - - bd6 - - vddgb vddgb - - bc8 - - i testmd0n - - av38 - - vss vss - - bc7 - - i pdn - - table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 243 1036-pin ftsbga devices have been discontinued. bd5 - - i atrefclk - - bd4 - - i testclk - - bd3 - - i btrefclk - - bc3 - - i tstat1b - - av13 - - i tstat0b - - bb7 - - i tsclkb - - bc6 - - o rstat1b - - bc4 - - o rstat0b - - bc5 - - o rsclkb - - aw8 - - vss vss - - aw15 - - vddob vddob_d - - ay15 - - o hdoutp_d - hsp_1 ba15 - - o hdoutn_d - hsn_1 bb15 - - vddob vddob_d - - ay14 - - i hdinp_d - hsp_2 aw10 - - vss vss - - ba14 - - i hdinn_d - hsn_2 av10 - - vdd_ana vdd_ana - - bb14 - - vddib vddib_d - - aw12 - - vss vss - - aw13 - - vddob vddob_c - - ay13 - - o hdoutp_c - hsp_3 ba13 - - o hdoutn_c - hsn_3 bb13 - - vddob vddob_c - - ay12 - - i hdinp_c - hsp_4 aw14 - - vss vss - - ba12 - - i hdinn_c - hsn_4 av12 - - vdd_ana vdd_ana - - bb12 - - vddib vddib_c - - bc9 - - vss vss - - aw11 - - vddob vddob_b - - ay11 - - o hdoutp_b - hsp_5 ba11 - - o hdoutn_b - hsn_5 bb11 - - vddob vddob_b - - av14 - - vdd_ana vdd_ana - - ay10 - - i hdinp_b - hsp_6 bc10 - - vss vss - - ba10 - - i hdinn_b - hsn_6 bb10 - - vddib vddib_b - - bd9 - - vss vss - - aw9 - - vddob vddob_a - - ay9 - - o hdoutp_a - hsp_7 ba9 - - o hdoutn_a - hsn_7 table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 244 1036-pin ftsbga devices have been discontinued. bb9 - - vddob vddob_a - - av8 - - vdd_ana vdd_ana - - ay8 - - i hdinp_a - hsp_8 bd10 - - vss vss - - ba8 - - i hdinn_a - hsn_8 bb8 - - vddib vddib_a - - aw7 - - i refclkp - hsp_9 ay7 - - i refclkn - hsn_9 ba7 - - o rextn - - av11 - - o rext - - aw4 - - i atstat1n - r1c au6 - - i atstat0n - r2c aw3 - - i atstat1p - r1t av6 - - i atstat0p - r2t av3 - - i atsclkn - r3c t6 - - vdd33 vdd33 - - av9 - - i/o alvctap5 - - t7 - - vdd33 vdd33 - - av2 - - i atsclkp - r3t ay2 - - i btsclkn - r4c ar6 - - i/o blvctap5 - - aw2 - - i btsclkp - r4t bc1 - - vss vss - - at4 - - i btstat1n - r5c bc2 - - vss vss - - bb5 - - i btstat0n - r6c at3 - - i btstat1p - r5t bb6 - - i btstat0p - r6t au38 - - vdd15 vdd15 - - av16 - - vdd15 vdd15 - - ar5 - - o brstat1n - r7c bc22 - - vss vss - - ba1 - - o brstat0n - r8c ar4 - - o brstat1p - r7t ay1 - - o brstat0p - r8t ap5 - - o brsclkn - r9c w6 - - vdd33 vdd33 - - aw1 - - o arsclkn - r10c w7 - - vdd33 vdd33 - - ap4 - - o brsclkp - r9t av1 - - o arsclkp - r10t bc43 - - vss vss - - an6 - - o arstat1n - r11c table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 245 1036-pin ftsbga devices have been discontinued. ba5 - - o arstat0n - r12c bc44 - - vss vss - - an5 - - o arstat1p - r11t ba6 - - o arstat0p - r12t av19 - - vdd15 vdd15 - - av28 - - vdd15 vdd15 - - au1 - - i reslo - - ap1 - - i reshi - - bd1 - - vss vss - - ar1 - - i ref14 - - ba2 - - i ref10 - - ab6 - - vdd33 vdd33 - - ab7 - - vdd33 vdd33 - - am6 - - o btdat15n - r13c bd2 - - vss vss - - ba4 - - o btdat14n - r14c am5 - - o btdat15p - r13t ba3 - - o btdat14p - r14t am4 - - o btdat13n - r15c av31 - - vdd15 vdd15 - - ay4 - - o btdat12n - r16c am3 - - o btdat13p - r15t av34 - - vdd15 vdd15 - - ay3 - - o btdat12p - r16t al5 - - o btdat11n - r17c bd11 - - vss vss - - aw5 - - o btdat10n - r18c al4 - - o btdat11p - r17t aw6 - - o btdat10p - r18t af6 - - vdd33 vdd33 - - al3 - - o btdat9n - r19c af7 - - vdd33 vdd33 - - av5 - - o btdat8n - r20c al2 - - o btdat9p - r19t av4 - - o btdat8p - r20t bd22 - - vss vss - - ak6 - - o btctln - r21c bd33 - - vss vss - - au5 - - o btdclkn - r22c ak5 - - o btctlp - r21t au4 - - o btdclkp - r22t av36 - - vdd15 vdd15 - - ak4 - - vdda_spia vdda_spia - - table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 246 1036-pin ftsbga devices have been discontinued. av37 - - vdd15 vdd15 - - ak3 - - vss vss - - au3 - - o btdat7n - r23c aj6 - - o btdat6n - r24c bd43 - - vss vss - - au2 - - o btdat7p - r23t aj5 - - o btdat6p - r24t aj4 - - o btdat5n - r25c ah6 - - vdd33 vdd33 - - at6 - - o btdat4n - r26c aj3 - - o btdat5p - r25t ah7 - - vdd33 vdd33 - - at5 - - o btdat4p - r26t ah5 - - o btdat3n - r27c at2 - - o btdat2n - r28c bd44 - - vss vss - - ah4 - - o btdat3p - r27t at1 - - o btdat2p - r28t ah3 - - o btdat1n - r29c ay5 - - vdd15 vdd15 - - ar3 - - o btdat0n - r30c ah2 - - o btdat1p - r29t ay6 - - vdd15 vdd15 - - ap3 - - o btdat0p - r31t ag6 - - i brdclkn - r32c ar2 - - i brdat15n - r33c ag5 - - i brdclkp - r32t ap2 - - i brdat15p - r33t af1 - - i/o blvctap1 - - al6 - - vdd33 vdd33 - - an4 - - i brdat14n - r34c al7 - - vdd33 vdd33 - - ag4 - - i brdat13n - r35c an3 - - i brdat14p - r34t ag3 - - i brdat13p - r35t am2 - - i brdat12n - r36c af3 - - i brdat11n - r37c am1 - - i brdat12p - r36t af2 - - i brdat11p - r37t al1 - - i brdat10n - r38c af4 - - i/o blvctap2 - - ak1 - - i brdat10p - r38t ae6 - - i brdat9n - r39c table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 247 1036-pin ftsbga devices have been discontinued. ak2 - - i brdat8n - r40c ae5 - - i brdat9p - r39t aj2 - - i brdat8p - r40t ae4 - - i brctln - r41c an2 - - i/o blvctap3 - - ae3 - - i brctlp - r41t ap6 - - vdd33 vdd33 - - aj1 - - i brdat7n - r42c ap7 - - vdd33 vdd33 - - ad6 - - i brdat6n - r43c ah1 - - i brdat7p - r42t ad5 - - i brdat6p - r43t ag2 - - i brdat5n - r44c ad4 - - i brdat4n - r45c ag1 - - i brdat5p - r44t ad3 - - i brdat4p - r45t af5 - - i/o blvctap4 - - ac6 - - i brdat3n - r46c ae2 - - i brdat2n - r47c ac5 - - i brdat3p - r46t ae1 - - i brdat2p - r47t ac4 - - i brdat1n - r48c ad2 - - i brdat0n - r49c ac3 - - i brdat1p - r48t ad1 - - i brdat0p - r49t w1 - - vss vss - - v1 - - vdda_spib vdda_spib - - ac1 - - o atdat15n - r50c u1 - - vss vss - - ac2 - - o atdat15p - r50t aa1 - - o atdat14n - r51c aa2 - - o atdat14p - r51t ab2 - - o atdat13n - r52c aa3 - - o atdat12n - r53c ab3 - - o atdat13p - r52t aa4 - - o atdat12p - r53t y1 - - o atdat11n - r54c v2 - - o atdat10n - r55c y2 - - o atdat11p - r54t u2 - - o atdat10p - r55t y3 - - o atdat9n - r56c ab5 - - o atdat8n - r57c y4 - - o atdat9p - r56t table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 248 1036-pin ftsbga devices have been discontinued. ab4 - - o atdat8p - r57t w2 - - o atctln - r58c aa5 - - o atdclkn - r59c w3 - - o atctlp - r58t y5 - - o atdclkp - r59t w4 - - o atdat7n - r60c aa6 - - o atdat6n - r61c w5 - - o atdat7p - r60t y6 - - o atdat6p - r61t t1 - - o atdat5n - r62c v3 - - o atdat4n - r63c r1 - - o atdat5p - r62t u3 - - o atdat4p - r63t t2 - - o atdat3n - r64c v4 - - o atdat2n - r65c r2 - - o atdat3p - r64t u4 - - o atdat2p - r65t t3 - - o atdat1n - r66c r4 - - o atdat0n - r67c r3 - - o atdat1p - r66t r5 - - o atdat0p - r67t t4 - - vss vss - - u5 - - vdda_spic vdda_spic - - u6 - - vss vss - - p1 - - i ardclkn - r68c v5 - - i ardat15n - r69c p2 - - i ardclkp - r68t v6 - - i ardat15p - r69t t5 - - i/o alvctap1 - - m3 - - i ardat14n - r70c p3 - - i ardat13n - r71c m4 - - i ardat14p - r70t p4 - - i ardat13p - r71t p5 - - i ardat12n - r72c n1 - - i ardat11n - r73c p6 - - i ardat12p - r72t n2 - - i ardat11p - r73t r6 - - i/o alvctap2 - - n3 - - i ardat10n - r74c n5 - - i ardat9n - r75c n4 - - i ardat10p - r74t n6 - - i ardat9p - r75t m1 - - i ardat8n - r76c table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 249 1036-pin ftsbga devices have been discontinued. l2 - - i arctln - r77c m2 - - i ardat8p - r76t l3 - - i arctlp - r77t g1 - - i/o alvctap3 - - m6 - - i ardat7n - r78c k1 - - i ardat6n - r79c m5 - - i ardat7p - r78t k2 - - i ardat6p - r79t k3 - - i ardat5n - r80c j1 - - i ardat4n - r81c j3 - - i ardat5p - r80t j2 - - i ardat4p - r81t h3 - - i/o alvctap4 - - h1 - - i ardat3n - r82c l5 - - i ardat2n - r83c h2 - - i ardat3p - r82t l4 - - i ardat2p - r83t g2 - - i ardat1n - r84c k4 - - i ardat0n - r85c g3 - - i ardat1p - r84t j4 - - i ardat0p - r85t l6 - - vdda_spid vdda_spid - - k5 - - vss vss - - f1 - - i tstat1a - - l7 - - i tstat0a - - e1 - - i tsclka - - d4 - - vss vss - - h4 - - o rstat1a - - d1 - - o rstat0a - - k6 - - o rsclka - - f2 - - i/o pmia17 - - j5 - - i/o pmia16 - - c4 - - i/o pmia15 - - g4 - - i/o pmia14 - - e2 - - i/o pmia13 - - e5 - - vss vss - - g5 - - i/o pmia12 - - f3 - - i/o pmia11 - - g9 - - vss vss - - j6 - - i/o pmia10 - - f4 - - i/o pmia9 - - h5 - - i/o pmia8 - - f6 - - vddh vddh - - table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 250 1036-pin ftsbga devices have been discontinued. e3 - - i/o pmiwn - - d2 - - i/o pmirn - - e4 - - i/o pmia7 - - d3 - - vref refi_1 - - g13 - - vss vss - - g6 - - i/o pmia6 - - g15 - - vss vss - - h6 - - i/o pmia5 - - h7 - - i/o pmia4 - - c1 - - i/o pmia3 - - g7 - - vddh vddh - - c3 - - i/o pmia2 - - f5 - - i/o pmia1 - - e6 - - i/o pmia0 - - k7 - - vss vss - - c2 - - i ext_1k - - g10 - - vddh vddh - - m7 - - vss vss - - p7 - - vss vss - - d7 - - i/o pmid35 - - d5 - - i/o pmid34 - - g12 - - vddh vddh - - c5 - - i/o pmid33 - - d6 - - i/o pmid32 - - g8 - - i/o pmid31 - - f7 - - i/o pmid30 - - c6 - - i/o pmid29 - - e7 - - i/o pmid28 - - g14 - - vddh vddh - - d8 - - i/o pmid27 - - b3 - - i/o pmid26 - - e8 - - i/o pmid25 - - b4 - - i/o pmid24 - - b9 - - i/o pmid23 - - a3 - - i/o pmid22 - - c7 - - i/o pmid21 - - a4 - - i/o pmid20 - - g16 - - vddh vddh - - c8 - - i/o pmid19 - - a9 - - i/o pmid18 - - b5 - - i/o pmid17 - - c10 - - i/o pmid16 - - d10 - - vref refi_2 - - table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 251 1036-pin ftsbga devices have been discontinued. f8 - - i/o pmik - - b10 - - i/o pmikn - - d9 - - i/o pmid15 - - a10 - - i/o pmid14 - - e9 - - i/o pmid13 - - b11 - - i/o pmid12 - - c9 - - i/o pmid11 - - c11 - - i/o pmid10 - - j7 - - vddh vddh - - f9 - - i/o pmid9 - - d11 - - i/o pmid8 - - b6 - - i/o pmid7 - - e11 - - i/o pmid6 - - b7 - - i/o pmid5 - - c12 - - i/o pmid4 - - n7 - - vddh vddh - - a5 - - i/o pmid3 - - d12 - - i/o pmid2 - - b8 - - i/o pmid1 - - b12 - - i/o pmid0 - - a12 - - vref refi_3 - - c13 - - i/o pmic - - d13 - - i/o pmicn - - a7 - - i/o pmiq35 - - b13 - - i/o pmiq34 - - a8 - - i/o pmiq33 - - a13 - - i/o pmiq32 - - a6 - - i/o pmiq31 - - c14 - - i/o pmiq30 - - f11 - - i/o pmiq29 - - d14 - - i/o pmiq28 - - g11 - - i/o pmiq27 - - b14 - - i/o pmiq26 - - f10 - - i/o pmiq25 - - a14 - - i/o pmiq24 - - e10 - - i/o pmiq23 - - c15 - - i/o pmiq22 - - f12 - - i/o pmiq21 - - d15 - - i/o pmiq20 - - e12 - - i/o pmiq19 - - b15 - - i/o pmiq18 - - f13 - - i/o pmiq17 - - a15 - - i/o pmiq16 - - table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 252 1036-pin ftsbga devices have been discontinued. e13 - - i/o mcrefclk - - c16 - - i/o spare_2 - - f14 - - i/o pmiq15 - - d16 - - vref refi_4 - - e14 - - i/o pmiq14 - - b16 - - i/o pmiq13 - - f15 - - i/o pmiq12 - - a16 - - vdda_pll vdda_pll - - e15 - - i/o pmiq11 - - c17 - - vss vss - - f16 - - i/o pmiq10 - - d17 - - i/o pmiq9 - - e16 - - i/o pmiq8 - - b17 - - i/o pmiq7 - - f17 - - i/o pmiq6 - - a17 - - i/o pmiq5 - - e17 - - i/o pmiq4 - - a18 - - i/o pmiq3 - - d18 - - i/o pmiq2 - - b18 - - i/o pmiq1 - - c18 - - i/o pmiq0 - - a19 - - vdd33 vdd33_fpgapll - - b19 - - vdd33 vdd33_fpgapll - - e18 1 (tc) 7 io pt47d pll_ck2c/ppll l185c g17 1 (tc) - vddio1 vddio1 - - f18 1 (tc) 7 io pt47c pll_ck2t/ppll l185t c19 1 (tc) 7 io pt46d - l187c ay39 - - vdd15 vdd15 - - e21 1 (tc) 7 io pt46b - l188c d19 1 (tc) 7 io pt46c - l187t f21 1 (tc) 7 io pt46a - l188t e19 1 (tc) 7 io pt45d vref_1_07 l189c l1 - - vss vss - - f19 1 (tc) 7 io pt45c - l189t c20 1 (tc) 8 io pt44d - l191c g18 1 (tc) - vddio1 vddio1 - - e23 1 (tc) 8 io pt44b - l192c d20 1 (tc) 8 io pt44c - l191t f23 1 (tc) 8 io pt44a - l192t e20 1 (tc) 8 io pt43d - l193c ay40 - - vdd15 vdd15 - - e24 1 (tc) 8 io pt43b - l194c f20 1 (tc) 8 io pt43c - l193t table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 253 1036-pin ftsbga devices have been discontinued. f24 1 (tc) 8 io pt43a - l194t b20 1 (tc) 8 io pt42d vref_1_08 l195c l44 - - vss vss - - f22 1 (tc) 8 io pt42b - l196c a20 1 (tc) 8 io pt42c - l195t g22 1 (tc) 8 io pt42a - l196t c21 1 (tc) 9 io pt41d - l197c g21 1 (tc) - vddio1 vddio1 - - e26 1 (tc) 9 io pt41b - l198c d21 1 (tc) 9 io pt41c - l197t f26 1 (tc) 9 io pt41a - l198t b21 1 (tc) 9 io pt40d - l199c bb3 - - vdd15 vdd15 - - e25 1 (tc) 9 io pt40b - l200c a21 1 (tc) 9 io pt40c vref_1_09 l199t f25 1 (tc) 9 io pt40a - l200t d22 1 (tc) 9 io pt39d - l201c m38 - - vss vss - - e28 1 (tc) 9 io pt39b - l202c e22 1 (tc) 9 io pt39c - l201t f28 1 (tc) 9 io pt39a - l202t c22 1 (tc) 10 io pt38d - l203c g24 1 (tc) - vddio1 vddio1 - - e29 1 (tc) 10 io pt38b - l204c b22 1 (tc) 10 io pt38c vref_1_10 l203t f29 1 (tc) 10 io pt38a - l204t c23 1 (tc) 10 io pt37d - l205c bb4 - - vdd15 vdd15 - - e27 1 (tc) 10 io pt37b - l206c d23 1 (tc) 10 io pt37c - l205t f27 1 (tc) 10 io pt37a - l206t b23 1 (tc) 10 io pt36d - l207c r38 - - vss vss - - a23 1 (tc) 10 io pt36c - l207t c24 1 (tc) 1 io pt35d - l209c g27 1 (tc) - vddio1 vddio1 - - c31 1 (tc) 1 io pt35b - l210c d24 1 (tc) 1 io pt35c - l209t d31 1 (tc) 1 io pt35a - l210t b24 1 (tc) 1 io pt34d vref_1_01 l211c bb41 - - vdd15 vdd15 - - e31 1 (tc) 1 io pt34b - l212c a24 1 (tc) 1 io pt34c - l211t table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 254 1036-pin ftsbga devices have been discontinued. f31 1 (tc) 1 io pt34a - l212t c25 1 (tc) 1 io pt33d - l213c v7 - - vss vss - - e30 1 (tc) 1 io pt33b - l214c d25 1 (tc) 1 io pt33c - l213t f30 1 (tc) 1 io pt33a - l214t b25 1 (tc) 2 io pt32d - l215c g28 1 (tc) - vddio1 vddio1 - - e32 1 (tc) 2 io pt32b - l216c a25 1 (tc) 2 io pt32c vref_1_02 l215t f32 1 (tc) 2 io pt32a - l216t c26 1 (tc) 2 io pt31d - l217c bb42 - - vdd15 vdd15 - - d33 1 (tc) 2 io pt31b - l218c d26 1 (tc) 2 io pt31c - l217t e33 1 (tc) 2 io pt31a - l218t b26 1 (tc) 2 io pt30d - l219c v38 - - vss vss - - f33 1 (tc) 2 io pt30b - l220c a26 1 (tc) 2 io pt30c - l219t g33 1 (tc) 2 io pt30a - l220t c27 1 (tc) 3 io pt29d - l221c e34 1 (tc) 3 io pt29b - l222c d27 1 (tc) 3 io pt29c vref_1_03 l221t f34 1 (tc) 3 io pt29a - l222t b27 1 (tc) 3 io pt28d - l223c e35 1 (tc) 3 io pt28b - l224c a27 1 (tc) 3 io pt28c - l223t f35 1 (tc) 3 io pt28a - l224t c28 1 (tc) 3 io pt27d - l225c aa7 - - vss vss - - c35 1 (tc) 3 io pt27b - l226c d28 1 (tc) 3 io pt27c - l225t d35 1 (tc) 3 io pt27a - l226t b28 1 (tc) 4 io pt26d - l227c a37 1 (tc) 4 io pt26b - l228c a28 1 (tc) 4 io pt26c - l227t b37 1 (tc) 4 io pt26a - l228t c29 1 (tc) 4 io pt25d - l229c e36 1 (tc) 4 io pt25b - l230c d29 1 (tc) 4 io pt25c - l229t f36 1 (tc) 4 io pt25a - l230t b29 1 (tc) 4 io pt24d - l231c table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 255 1036-pin ftsbga devices have been discontinued. aa38 - - vss vss - - c37 1 (tc) 4 io pt24b - l232c a29 1 (tc) 4 io pt24c vref_1_04 l231t d37 1 (tc) 4 io pt24a - l232t a30 1 (tc) 5 io pt23d ptck1c l233c e37 1 (tc) 5 io pt23b - l234c b30 1 (tc) 5 io pt23c ptck1t l233t f37 1 (tc) 5 io pt23a - l234t d30 1 (tc) 5 io pt22d ptck0c l235c a38 1 (tc) 5 io pt22b - l236c c30 1 (tc) 5 io pt22c ptck0t l235t b38 1 (tc) 5 io pt22a - l236t a31 1 (tc) 5 io pt21d vref_1_05 l237c c38 1 (tc) 5 io pt21b - l238c b31 1 (tc) 5 io pt21c - l237t d38 1 (tc) 5 io pt21a - l238t a32 1 (tc) 6 io pt20d - l239c e38 1 (tc) 6 io pt20b - l240c b32 1 (tc) 6 io pt20c - l239t f38 1 (tc) 6 io pt20a - l240t c32 1 (tc) 6 io pt19d - l241c e43 1 (tc) 6 io pt19b - l242c d32 1 (tc) 6 io pt19c vref_1_06 l241t e44 1 (tc) 6 io pt19a - l242t a34 0 (tl) 1 io pt18d mpi_rtry_n l243c a33 - - vss vss - - f44 0 (tl) 1 io pt18b - l244c b34 0 (tl) 1 io pt18c mpi_ack_n l243t f43 0 (tl) 1 io pt18a - l244t b33 0 (tl) 1 io pt17d - l245c g38 0 (tl) - vddio0 vddio0 - - f41 0 (tl) 1 io pt17b - l246c c33 0 (tl) 1 io pt17c vref_0_01 l245t f42 0 (tl) 1 io pt17a - l246t c34 0 (tl) 1 io pt16d m0 l247c f40 - - vdd15 vdd15 - - g39 0 (tl) 2 io pt16b - l248c d34 0 (tl) 1 io pt16c m1 l247t g40 0 (tl) 2 io pt16a - l248t a35 0 (tl) 2 io pt15d mpi_clk l249c a43 - - vss vss - - h40 0 (tl) 2 io pt15b - l250c b35 0 (tl) 2 io pt15c a21/mpi_burst_n l249t table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 256 1036-pin ftsbga devices have been discontinued. h39 0 (tl) 2 io pt15a - l250t a36 0 (tl) 2 io pt14d m2 l251c p38 0 (tl) - vddio0 vddio0 - - b36 0 (tl) 2 io pt14c m3 l251t c36 0 (tl) 2 io pt13d vref_0_02 l253c g19 - - vdd15 vdd15 - - g41 0 (tl) 2 io pt13b - l254c d36 0 (tl) 2 io pt13c mpi_tea_n l253t g42 0 (tl) 2 io pt13a - l254t a39 0 (tl) 3 io pt12d - l255c a44 - - vss vss - - a40 0 (tl) 3 io pt12c - l255t a41 0 (tl) 3 io pt11d vref_0_03 l257c u38 0 (tl) - vddio0 vddio0 - - g43 0 (tl) 3 io pt11b - l258c a42 0 (tl) 3 io pt11c - l257t g44 0 (tl) 3 io pt11a - l258t b39 0 (tl) 3 io pt10d d0 l259c g25 - - vdd15 vdd15 - - b40 0 (tl) 3 io pt10c tms l259t b41 0 (tl) 4 io pt9d a20/mpi_bdip_n l261c b1 - - vss vss - - h44 0 (tl) 4 io pt9b - l262c b42 0 (tl) 4 io pt9c a19/mpi_tsz1 l261t h43 0 (tl) 4 io pt9a - l262t c39 0 (tl) 4 io pt8d a18/mpi_tsz0 l263c c40 0 (tl) 4 io pt8c d3 l263t d39 0 (tl) 4 io pt7d vref_0_04 l265c j42 0 (tl) 4 io pt7b - l266c d40 0 (tl) 4 io pt7c - l265t j41 0 (tl) 4 io pt7a - l266t e39 0 (tl) 5 io pt6d d1 l267c f39 0 (tl) 5 io pt6c d2 l267t c41 0 (tl) 5 io pt5d - l269c j40 0 (tl) 5 io pt5b - l270c d41 0 (tl) 5 io pt5c vref_0_05 l269t j39 0 (tl) 5 io pt5a - l270t e41 0 (tl) 5 io pt4d tdi l271c e42 0 (tl) 5 io pt4c tck l271t c43 0 (tl) 6 io pt3d - l273c h42 0 (tl) 6 io pt3b - l274c d43 0 (tl) 6 io pt3c vref_0_06 l273t h41 0 (tl) 6 io pt3a - l274t table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 257 1036-pin ftsbga devices have been discontinued. c44 0 (tl) 6 io pt2d pll_ck1c/ppll l275c d44 0 (tl) 6 io pt2c pll_ck1t/ppll l275t k38 - - o pcfg_mpi_irq cfg_irq_n/mpi_i rq_n - k39 - - io pcclk cclk - k40 - - io pdone done - k41 - - vdd33 vdd33_fpgapll - - note: all differential pairs use adjacent balls. table 87. 1036 ftsbga pin table (continued) fte1036 ball vddio bank vref group i/o pin description additional function fte1036 pair lattice semiconductor orca orspi4 data sheet 258 1036-pin ftsbga devices have been discontinued. package information package thermal characteristics summary there are three thermal parameters that are in common use: ja , jc, and jc. it should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system air?w. ja this is the thermal resistance from junction to ambient (theta-ja, r-theta, etc.): (1) where t j is the junction temperature, t a, is the ambient air temperature, and q is the chip power. experimentally, ja is determined when a special thermal test die is assembled into the package of interest, and the part is mounted on the thermal test board. the diodes on the test chip are separately calibrated in an oven. the package/board is placed either in a jedec natural convection box or in the wind tunnel, the latter for forced con- vection measurements. a controlled amount of power (q) is dissipated in the test chip s heater resistor, the chip s temperature (t j ) is determined by the forward drop on the diodes, and the ambient temperature (t a ) is noted. note that ja is expressed in units of ?/w. jc this jedec designated parameter correlates the junction temperature to the case temperature. it is generally used to infer the junction temperature while the device is operating in the system. it is not considered a true thermal resistance and it is de?ed by: (2) where t c is the case temperature at top dead center, t j is the junction temperature, and q is the chip power. dur- ing the ja measurements described above, besides the other parameters measured, an additional temperature reading, t c , is made with a thermocouple attached at top-dead-center of the case. jc is also expressed in units of ?/w. jc this is the thermal resistance from junction to case. it is most often used when attaching a heat sink to the top of the package. it is de?ed by: (3) the parameters in this equation have been de?ed above. however, the measurements are performed with the case of the part pressed against a water-cooled heat sink to draw most of the heat generated by the chip out the top of the package. it is this difference in the measurement process that differentiates jc from jc. jc is a true thermal resistance and is expressed in units of ?/w. jb this is the thermal resistance from junction to board. it is de?ed by: (4) where t b is the temperature of the board adjacent to a lead measured with a thermocouple. the other parameters on the right-hand side have been de?ed above. this is considered a true thermal resistance, and the measure- ja t j t a q ------------------- = jc t j t c q ------------------- = jc t j t c q ------------------- = jb t j t b q ------------------- = lattice semiconductor orca orspi4 data sheet 259 1036-pin ftsbga devices have been discontinued. ment is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. note that jb is expressed in units of ?/w and that this parameter and the way it is measured are still being dis- cussed by the jedec committee. fpsc maximum junction temperature once the power dissipated by the fpsc has been determined, the maximum junction temperature of the fpsc can be found. this is needed to determine if speed derating of the device from the 85 ? junction temperature used in all of the delay tables is needed. using the maximum ambient temperature, t amax , and the power dissipated by the device, q (expressed in ?), the maximum junction temperature is approximated by: t jmax = t amax + (q ? ja ) package thermal characteristics the thermal characteristics of the 1036-ball ftsbga and the 1156-ball fpbga used for the orspi4 are available at the thermal management section of the lattice semiconductor web site at www .latticesemi.com . heat sink vendors for bga packages the estimated worst-case power requirements for the orspi4 is in the 8 w to 10 w range. consequently, for most applications an external heat sink will be required. table 88 lists, in alphabetical order, heat sink vendors who advertise heat sinks aimed at the bga market. table 88. heat sink vendors package parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. figure 102. package parasitics vendor location phone aavid thermalloy concord, nh (603) 224-9988 chip coolers warwick, ri (800) 227-0254 ierc burbank, ca (818) 842-7277 r-theta buffalo, ny (800) 388-5428 sanyo denki torrance, ca (310) 783-5400 wake?ld thermal solutions pelham, nh (800) 325-1426 pad n board pads c m c 1 l sw r w l sl l mw c 2 c 1 l ml c 2 pad n + 1 l sw r w l sl circuit pad n+1 pad n package pads lattice semiconductor orca orspi4 data sheet 260 1036-pin ftsbga devices have been discontinued. package outline drawings package outline drawings for the 1036-ball ftsbga and the 1156-ball fpbga used for the orspi4 are available in the package diagrams section of the lattice semiconductor web site at www .latticesemi.com . lattice semiconductor orca orspi4 data sheet 261 1036-pin ftsbga devices have been discontinued. ordering information table 89. device type options table 90. commercial ordering information 1 table 91. industrial ordering information 1 table 92. pb-free commercial ordering information 1 device voltage orspi4 1.5 v internal 3.3 v/2.5 v/1.8 v/ 1.5 v i/o device family part number speed grade package type ball count grade orspi4 orspi4-3fte1036c 2 3 ftsbga 1036 c orspi4-2fte1036c 2 2c orspi4-1fte1036c 2 1c orspi4-3f1156c 3 fpbga 1156 c orspi4-2f1156c 2 c orspi4-1f1156c 1 c device family part number speed grade package type ball count grade orspi4 ORSPI4-2FTE1036I 2 2 ftsbga 1036 i orspi4-1fte1036i 2 1i orspi4-2f1156i 2 fpbga 1156 i orspi4-1f1156i 1 i device family part number speed grade package type ball count grade orspi4 orspi4-3fn1156c 3 pb-free fpbga 1156 c orspi4-2fn1156c 2 c orspi4-1fn1156c 1 c device family orspi4 package grade xxxxxx x speed grade c = commercial i = industrial x xx optional suffix blank = production es = engineering samples f1156 = 1156-ball fpbga (fine-pitch bga) - fn1156 = lead-free1156-ball fpbga (fine-pitch bga) fte1036 = 1036-ball ftsbga (thermally enhanced fine-pitch thin bga) lattice semiconductor orca orspi4 data sheet 262 1036-pin ftsbga devices have been discontinued. table 93. pb-free industrial ordering information 1 revision history device family part number speed grade package type ball count grade orspi4 orspi4-2fn1156i 2 pb-free fpbga 1156 i orspi4-1fn1156i 1 i 1. for all but the slowest commercial speed grade, the speed grades on these devices are dual marked. for example, the commer- cial speed grade -3xxxxxc is also marked with the industrial grade -2xxxxxi. the commercial grade is always one speed grade faster than the associated dual mark industrial grade. the slowest commercial speed grade is marked as commercial grade only. 2. discontinued per pcn#06x-09 in may 2009. date version change summary previous lattice releases. july 2004 02.0 phase-locked loops description has been updated. orspi transmit fpga/embedded core interface description has been updated. spia core transmit fpga interface in 32-bit mode. spia core transmit fpga interface in 64-bit mode, and table 4. spia core transmit fpga interface in 128-bit mode have been updated. link disable section has been updated. tx dpram section has been updated. port credit field update flow chart has been added and the description has been updated. calendar programming section has been updated to "after programming the calendar memory, the tx_cal_mem_sel bit is set to '0'." spia core receive fpga interface in 32-bit mode has been updated. rdi block description has been updated. far end loopback setup section has been added. orspi4 qdrii memory controller block diagram has been updated. fpga/embedded core signals has been updated. orspi4 memory controller interface to fpga - write timing diagram has been updated. orspi4 memory controller interface to qdrii: 4-word burst mode has been updated. orspi4 memory controller interface to fpga - read timing diagram has been updated. memory controller instruction latency section has been updated. memory map has been updated. orspi4 post con?uration standby current has been added. orspi4 serdes worst case power table has been updated with footnote 2. supported data rates has been updated. spi4.2 data interface has been added." timing reference points with respect to clock edge has been updated. data path interface timing for static alignment has been updated. status path interface oif-spi4-02.2 speci?ation timing (reference) has been updated. status path interface orspi4 timing in centered (oif) mode has been updated. status channel reference points with respect to clock edge has been updated. status path interface orspi4 timing in legacy mode has been updated. channel output jitter (3.125 gbits/s) has been updated. channel output jitter (2.5 gbits/s) has been updated." memory controller input/output timing speci?ation has been added. memory controller output timing speci?ation has been added. memory controller input timing speci?ation has been added. lattice semiconductor orca orspi4 data sheet 263 1036-pin ftsbga devices have been discontinued. october 2004 03.0 datasheet is now final status for production release of the device. clock rates under high performance memory controller for interface to external buffer memory has been updated to 175mhz ddr performance has been updated to 175mhz in the introduction section. fpga logic overview section has been updated. recommended operating conditions has been updated. orspi4 post-con?uration stabdby currenttable has been updated. orspi4 combined spia and spib worst case power table has been updated. orspi4 qdr memory controller worst case power table has been updated. orspi4 serdes worst case power table has been updated with footnote 2. supported data rates table has been updated. system timing reference points has been updated. spi4.2 timing points with respect to clock edge has been added. spi4.2 data interface table has been updated. spi4.2 receive timing points with respect to clock edge has been added." spi4.2 receive data interface timing has been updated. data path interface timing for static alignment has been updated. data path parameters for dynamic alignment has been updated. status channel reference points with respect to clock edge (lvds and lvttl i/os) has been updated. status path interface orspi4 timing in centered (oif) mode february 2005 04.0 status channel reference points with respect to clock edge (edge aligned legacy mode) has been updated. status path interface orspi4 timing in legacy mode has been updated. channel output jiffer (3.125 gbits/s) has been updated. channel output jitter (2.5 gbits/s) has been updated. hstl class i and ii section has been updated. hstl class ii dc operating speci?ations has been updated. supported data rtes (36-bit qdr-ii, 32 bit considered data) table has been updated. memory controller output timing speci?ations has been updated. memory controller input timing speci?ations have been updated. memory controller input timing speci?ations have been updated. recommended power supply connections section has been updated. recommended power supply filtering scheme section has been updated. commercial ordering information table and industrial ordering information table have been updated for production release of the orspi4. april 2005 05.0 released 1156-fpbga pb-free devices. october 2007 06.0 added 1036-ball ftsbga information per pcn#16a-07 (package conversion from 1036- fpsbga to 1036-ftsbga). may 2009 07.0 ordering part number information section was updated per pcn#06x-09 (1036-pin ftsbga package discontinuance). date version change summary |
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